Merge pull request #512 from Subv/fset

GPU: Corrected the FSET and I2F instructions.

src/video_core/engines/shader_bytecode.h

@@ -245,9 +245,9 @@ union Instruction {
         BitField<44, 1, u64> abs_b;
         BitField<45, 2, PredOperation> op;
         BitField<48, 4, PredCondition> cond;
+        BitField<52, 1, u64> bf;
         BitField<53, 1, u64> neg_b;
         BitField<54, 1, u64> abs_a;
-        BitField<52, 1, u64> bf;
         BitField<55, 1, u64> ftz;
         BitField<56, 1, u64> neg_imm;
     } fset;

src/video_core/renderer_opengl/gl_shader_decompiler.cpp

@@ -871,8 +871,7 @@ private:
             ASSERT_MSG(!instr.conversion.saturate_a, "Unimplemented");
 
             switch (opcode->GetId()) {
-            case OpCode::Id::I2I_R:
-            case OpCode::Id::I2F_R: {
+            case OpCode::Id::I2I_R: {
                 ASSERT_MSG(!instr.conversion.selector, "Unimplemented");
 
                 std::string op_a =
@@ -885,6 +884,17 @@ private:
                 regs.SetRegisterToInteger(instr.gpr0, instr.conversion.is_signed, 0, op_a, 1, 1);
                 break;
             }
+            case OpCode::Id::I2F_R: {
+                std::string op_a =
+                    regs.GetRegisterAsInteger(instr.gpr20, 0, instr.conversion.is_signed);
+
+                if (instr.conversion.abs_a) {
+                    op_a = "abs(" + op_a + ')';
+                }
+
+                regs.SetRegisterToFloat(instr.gpr0, 0, op_a, 1, 1);
+                break;
+            }
             case OpCode::Id::F2F_R: {
                 std::string op_a = regs.GetRegisterAsFloat(instr.gpr20);
 
@@ -1078,7 +1088,12 @@ private:
             std::string predicate = "(((" + op_a + ") " + comparator + " (" + op_b + ")) " +
                                     combiner + " (" + second_pred + "))";
 
-            regs.SetRegisterToFloat(instr.gpr0, 0, predicate + " ? 1.0 : 0.0", 1, 1);
+            if (instr.fset.bf) {
+                regs.SetRegisterToFloat(instr.gpr0, 0, predicate + " ? 1.0 : 0.0", 1, 1);
+            } else {
+                regs.SetRegisterToInteger(instr.gpr0, false, 0, predicate + " ? 0xFFFFFFFF : 0", 1,
+                                          1);
+            }
             break;
         }
         default: {