fermi_2d.h 10 KB

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  1. // SPDX-FileCopyrightText: Copyright 2018 yuzu Emulator Project
  2. // SPDX-License-Identifier: GPL-2.0-or-later
  3. #pragma once
  4. #include <array>
  5. #include <cstddef>
  6. #include <memory>
  7. #include "common/bit_field.h"
  8. #include "common/common_funcs.h"
  9. #include "common/common_types.h"
  10. #include "video_core/engines/engine_interface.h"
  11. #include "video_core/gpu.h"
  12. namespace Tegra {
  13. class MemoryManager;
  14. }
  15. namespace VideoCore {
  16. class RasterizerInterface;
  17. }
  18. namespace Tegra::Engines {
  19. namespace Blitter {
  20. class SoftwareBlitEngine;
  21. }
  22. /**
  23. * This Engine is known as G80_2D. Documentation can be found in:
  24. * https://github.com/envytools/envytools/blob/master/rnndb/graph/g80_2d.xml
  25. * https://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/nouveau/nv50/nv50_2d.xml.h
  26. */
  27. #define FERMI2D_REG_INDEX(field_name) \
  28. (offsetof(Tegra::Engines::Fermi2D::Regs, field_name) / sizeof(u32))
  29. class Fermi2D final : public EngineInterface {
  30. public:
  31. explicit Fermi2D(MemoryManager& memory_manager_);
  32. ~Fermi2D() override;
  33. /// Binds a rasterizer to this engine.
  34. void BindRasterizer(VideoCore::RasterizerInterface* rasterizer);
  35. /// Write the value to the register identified by method.
  36. void CallMethod(u32 method, u32 method_argument, bool is_last_call) override;
  37. /// Write multiple values to the register identified by method.
  38. void CallMultiMethod(u32 method, const u32* base_start, u32 amount,
  39. u32 methods_pending) override;
  40. enum class Origin : u32 {
  41. Center = 0,
  42. Corner = 1,
  43. };
  44. enum class Filter : u32 {
  45. Point = 0,
  46. Bilinear = 1,
  47. };
  48. enum class Operation : u32 {
  49. SrcCopyAnd = 0,
  50. ROPAnd = 1,
  51. Blend = 2,
  52. SrcCopy = 3,
  53. ROP = 4,
  54. SrcCopyPremult = 5,
  55. BlendPremult = 6,
  56. };
  57. enum class MemoryLayout : u32 {
  58. BlockLinear = 0,
  59. Pitch = 1,
  60. };
  61. enum class CpuIndexWrap : u32 {
  62. Wrap = 0,
  63. NoWrap = 1,
  64. };
  65. struct Surface {
  66. RenderTargetFormat format;
  67. MemoryLayout linear;
  68. union {
  69. BitField<0, 4, u32> block_width;
  70. BitField<4, 4, u32> block_height;
  71. BitField<8, 4, u32> block_depth;
  72. };
  73. u32 depth;
  74. u32 layer;
  75. u32 pitch;
  76. u32 width;
  77. u32 height;
  78. u32 addr_upper;
  79. u32 addr_lower;
  80. [[nodiscard]] constexpr GPUVAddr Address() const noexcept {
  81. return (GPUVAddr{addr_upper} << 32) | GPUVAddr{addr_lower};
  82. }
  83. };
  84. static_assert(sizeof(Surface) == 0x28, "Surface has incorrect size");
  85. enum class SectorPromotion : u32 {
  86. NoPromotion = 0,
  87. PromoteTo2V = 1,
  88. PromoteTo2H = 2,
  89. PromoteTo4 = 3,
  90. };
  91. enum class NumTpcs : u32 {
  92. All = 0,
  93. One = 1,
  94. };
  95. enum class RenderEnableMode : u32 {
  96. False = 0,
  97. True = 1,
  98. Conditional = 2,
  99. RenderIfEqual = 3,
  100. RenderIfNotEqual = 4,
  101. };
  102. enum class ColorKeyFormat : u32 {
  103. A16R56G6B5 = 0,
  104. A1R5G55B5 = 1,
  105. A8R8G8B8 = 2,
  106. A2R10G10B10 = 3,
  107. Y8 = 4,
  108. Y16 = 5,
  109. Y32 = 6,
  110. };
  111. union Beta4 {
  112. BitField<0, 8, u32> b;
  113. BitField<8, 8, u32> g;
  114. BitField<16, 8, u32> r;
  115. BitField<24, 8, u32> a;
  116. };
  117. struct Point {
  118. u32 x;
  119. u32 y;
  120. };
  121. enum class PatternSelect : u32 {
  122. MonoChrome8x8 = 0,
  123. MonoChrome64x1 = 1,
  124. MonoChrome1x64 = 2,
  125. Color = 3,
  126. };
  127. enum class NotifyType : u32 {
  128. WriteOnly = 0,
  129. WriteThenAwaken = 1,
  130. };
  131. enum class MonochromePatternColorFormat : u32 {
  132. A8X8R8G6B5 = 0,
  133. A1R5G5B5 = 1,
  134. A8R8G8B8 = 2,
  135. A8Y8 = 3,
  136. A8X8Y16 = 4,
  137. Y32 = 5,
  138. };
  139. enum class MonochromePatternFormat : u32 {
  140. CGA6_M1 = 0,
  141. LE_M1 = 1,
  142. };
  143. union Regs {
  144. static constexpr std::size_t NUM_REGS = 0x258;
  145. struct {
  146. u32 object;
  147. INSERT_PADDING_WORDS_NOINIT(0x3F);
  148. u32 no_operation;
  149. NotifyType notify;
  150. INSERT_PADDING_WORDS_NOINIT(0x2);
  151. u32 wait_for_idle;
  152. INSERT_PADDING_WORDS_NOINIT(0xB);
  153. u32 pm_trigger;
  154. INSERT_PADDING_WORDS_NOINIT(0xF);
  155. u32 context_dma_notify;
  156. u32 dst_context_dma;
  157. u32 src_context_dma;
  158. u32 semaphore_context_dma;
  159. INSERT_PADDING_WORDS_NOINIT(0x1C);
  160. Surface dst;
  161. CpuIndexWrap pixels_from_cpu_index_wrap;
  162. u32 kind2d_check_enable;
  163. Surface src;
  164. SectorPromotion pixels_from_memory_sector_promotion;
  165. INSERT_PADDING_WORDS_NOINIT(0x1);
  166. NumTpcs num_tpcs;
  167. u32 render_enable_addr_upper;
  168. u32 render_enable_addr_lower;
  169. RenderEnableMode render_enable_mode;
  170. INSERT_PADDING_WORDS_NOINIT(0x4);
  171. u32 clip_x0;
  172. u32 clip_y0;
  173. u32 clip_width;
  174. u32 clip_height;
  175. BitField<0, 1, u32> clip_enable;
  176. BitField<0, 3, ColorKeyFormat> color_key_format;
  177. u32 color_key;
  178. BitField<0, 1, u32> color_key_enable;
  179. BitField<0, 8, u32> rop;
  180. u32 beta1;
  181. Beta4 beta4;
  182. Operation operation;
  183. union {
  184. BitField<0, 6, u32> x;
  185. BitField<8, 6, u32> y;
  186. } pattern_offset;
  187. BitField<0, 2, PatternSelect> pattern_select;
  188. INSERT_PADDING_WORDS_NOINIT(0xC);
  189. struct {
  190. BitField<0, 3, MonochromePatternColorFormat> color_format;
  191. BitField<0, 1, MonochromePatternFormat> format;
  192. u32 color0;
  193. u32 color1;
  194. u32 pattern0;
  195. u32 pattern1;
  196. } monochrome_pattern;
  197. struct {
  198. std::array<u32, 0x40> X8R8G8B8;
  199. std::array<u32, 0x20> R5G6B5;
  200. std::array<u32, 0x20> X1R5G5B5;
  201. std::array<u32, 0x10> Y8;
  202. } color_pattern;
  203. INSERT_PADDING_WORDS_NOINIT(0x10);
  204. struct {
  205. u32 prim_mode;
  206. u32 prim_color_format;
  207. u32 prim_color;
  208. u32 line_tie_break_bits;
  209. INSERT_PADDING_WORDS_NOINIT(0x14);
  210. u32 prim_point_xy;
  211. INSERT_PADDING_WORDS_NOINIT(0x7);
  212. std::array<Point, 0x40> prim_point;
  213. } render_solid;
  214. struct {
  215. u32 data_type;
  216. u32 color_format;
  217. u32 index_format;
  218. u32 mono_format;
  219. u32 wrap;
  220. u32 color0;
  221. u32 color1;
  222. u32 mono_opacity;
  223. INSERT_PADDING_WORDS_NOINIT(0x6);
  224. u32 src_width;
  225. u32 src_height;
  226. u32 dx_du_frac;
  227. u32 dx_du_int;
  228. u32 dx_dv_frac;
  229. u32 dy_dv_int;
  230. u32 dst_x0_frac;
  231. u32 dst_x0_int;
  232. u32 dst_y0_frac;
  233. u32 dst_y0_int;
  234. u32 data;
  235. } pixels_from_cpu;
  236. INSERT_PADDING_WORDS_NOINIT(0x3);
  237. u32 big_endian_control;
  238. INSERT_PADDING_WORDS_NOINIT(0x3);
  239. struct {
  240. BitField<0, 3, u32> block_shape;
  241. BitField<0, 5, u32> corral_size;
  242. BitField<0, 1, u32> safe_overlap;
  243. union {
  244. BitField<0, 1, Origin> origin;
  245. BitField<4, 1, Filter> filter;
  246. } sample_mode;
  247. INSERT_PADDING_WORDS_NOINIT(0x8);
  248. s32 dst_x0;
  249. s32 dst_y0;
  250. s32 dst_width;
  251. s32 dst_height;
  252. s64 du_dx;
  253. s64 dv_dy;
  254. s64 src_x0;
  255. s64 src_y0;
  256. } pixels_from_memory;
  257. };
  258. std::array<u32, NUM_REGS> reg_array;
  259. } regs{};
  260. struct Config {
  261. Operation operation;
  262. Filter filter;
  263. bool must_accelerate;
  264. s32 dst_x0;
  265. s32 dst_y0;
  266. s32 dst_x1;
  267. s32 dst_y1;
  268. s32 src_x0;
  269. s32 src_y0;
  270. s32 src_x1;
  271. s32 src_y1;
  272. };
  273. private:
  274. VideoCore::RasterizerInterface* rasterizer = nullptr;
  275. std::unique_ptr<Blitter::SoftwareBlitEngine> sw_blitter;
  276. MemoryManager& memory_manager;
  277. /// Performs the copy from the source surface to the destination surface as configured in the
  278. /// registers.
  279. void Blit();
  280. void ConsumeSinkImpl() override;
  281. };
  282. #define ASSERT_REG_POSITION(field_name, position) \
  283. static_assert(offsetof(Fermi2D::Regs, field_name) == position, \
  284. "Field " #field_name " has invalid position")
  285. ASSERT_REG_POSITION(object, 0x0);
  286. ASSERT_REG_POSITION(no_operation, 0x100);
  287. ASSERT_REG_POSITION(notify, 0x104);
  288. ASSERT_REG_POSITION(wait_for_idle, 0x110);
  289. ASSERT_REG_POSITION(pm_trigger, 0x140);
  290. ASSERT_REG_POSITION(context_dma_notify, 0x180);
  291. ASSERT_REG_POSITION(dst_context_dma, 0x184);
  292. ASSERT_REG_POSITION(src_context_dma, 0x188);
  293. ASSERT_REG_POSITION(semaphore_context_dma, 0x18C);
  294. ASSERT_REG_POSITION(dst, 0x200);
  295. ASSERT_REG_POSITION(pixels_from_cpu_index_wrap, 0x228);
  296. ASSERT_REG_POSITION(kind2d_check_enable, 0x22C);
  297. ASSERT_REG_POSITION(src, 0x230);
  298. ASSERT_REG_POSITION(pixels_from_memory_sector_promotion, 0x258);
  299. ASSERT_REG_POSITION(num_tpcs, 0x260);
  300. ASSERT_REG_POSITION(render_enable_addr_upper, 0x264);
  301. ASSERT_REG_POSITION(render_enable_addr_lower, 0x268);
  302. ASSERT_REG_POSITION(clip_x0, 0x280);
  303. ASSERT_REG_POSITION(clip_y0, 0x284);
  304. ASSERT_REG_POSITION(clip_width, 0x288);
  305. ASSERT_REG_POSITION(clip_height, 0x28c);
  306. ASSERT_REG_POSITION(clip_enable, 0x290);
  307. ASSERT_REG_POSITION(color_key_format, 0x294);
  308. ASSERT_REG_POSITION(color_key, 0x298);
  309. ASSERT_REG_POSITION(rop, 0x2A0);
  310. ASSERT_REG_POSITION(beta1, 0x2A4);
  311. ASSERT_REG_POSITION(beta4, 0x2A8);
  312. ASSERT_REG_POSITION(operation, 0x2AC);
  313. ASSERT_REG_POSITION(pattern_offset, 0x2B0);
  314. ASSERT_REG_POSITION(pattern_select, 0x2B4);
  315. ASSERT_REG_POSITION(monochrome_pattern, 0x2E8);
  316. ASSERT_REG_POSITION(color_pattern, 0x300);
  317. ASSERT_REG_POSITION(render_solid, 0x580);
  318. ASSERT_REG_POSITION(pixels_from_cpu, 0x800);
  319. ASSERT_REG_POSITION(big_endian_control, 0x870);
  320. ASSERT_REG_POSITION(pixels_from_memory, 0x880);
  321. #undef ASSERT_REG_POSITION
  322. } // namespace Tegra::Engines