shader_interpreter.cpp 19 KB

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  1. // Copyright 2014 Citra Emulator Project
  2. // Licensed under GPLv2 or any later version
  3. // Refer to the license.txt file included.
  4. #include <common/file_util.h>
  5. #include <nihstro/shader_bytecode.h>
  6. #include "video_core/pica.h"
  7. #include "shader.h"
  8. #include "shader_interpreter.h"
  9. using nihstro::OpCode;
  10. using nihstro::Instruction;
  11. using nihstro::RegisterType;
  12. using nihstro::SourceRegister;
  13. using nihstro::SwizzlePattern;
  14. namespace Pica {
  15. namespace Shader {
  16. void RunInterpreter(UnitState& state) {
  17. const auto& uniforms = g_state.vs.uniforms;
  18. const auto& swizzle_data = g_state.vs.swizzle_data;
  19. const auto& program_code = g_state.vs.program_code;
  20. // Placeholder for invalid inputs
  21. static float24 dummy_vec4_float24[4];
  22. while (true) {
  23. if (!state.call_stack.empty()) {
  24. auto& top = state.call_stack.back();
  25. if (state.program_counter == top.final_address) {
  26. state.address_registers[2] += top.loop_increment;
  27. if (top.repeat_counter-- == 0) {
  28. state.program_counter = top.return_address;
  29. state.call_stack.pop_back();
  30. } else {
  31. state.program_counter = top.loop_address;
  32. }
  33. // TODO: Is "trying again" accurate to hardware?
  34. continue;
  35. }
  36. }
  37. bool exit_loop = false;
  38. const Instruction instr = { program_code[state.program_counter] };
  39. const SwizzlePattern swizzle = { swizzle_data[instr.common.operand_desc_id] };
  40. static auto call = [](UnitState& state, u32 offset, u32 num_instructions,
  41. u32 return_offset, u8 repeat_count, u8 loop_increment) {
  42. state.program_counter = offset - 1; // -1 to make sure when incrementing the PC we end up at the correct offset
  43. ASSERT(state.call_stack.size() < state.call_stack.capacity());
  44. state.call_stack.push_back({ offset + num_instructions, return_offset, repeat_count, loop_increment, offset });
  45. };
  46. state.debug.max_offset = std::max<u32>(state.debug.max_offset, 1 + state.program_counter);
  47. auto LookupSourceRegister = [&](const SourceRegister& source_reg) -> const float24* {
  48. switch (source_reg.GetRegisterType()) {
  49. case RegisterType::Input:
  50. return &state.registers.input[source_reg.GetIndex()].x;
  51. case RegisterType::Temporary:
  52. return &state.registers.temporary[source_reg.GetIndex()].x;
  53. case RegisterType::FloatUniform:
  54. return &uniforms.f[source_reg.GetIndex()].x;
  55. default:
  56. return dummy_vec4_float24;
  57. }
  58. };
  59. switch (instr.opcode.Value().GetInfo().type) {
  60. case OpCode::Type::Arithmetic:
  61. {
  62. const bool is_inverted = (0 != (instr.opcode.Value().GetInfo().subtype & OpCode::Info::SrcInversed));
  63. const int address_offset = (instr.common.address_register_index == 0)
  64. ? 0 : state.address_registers[instr.common.address_register_index - 1];
  65. const float24* src1_ = LookupSourceRegister(instr.common.GetSrc1(is_inverted) + (!is_inverted * address_offset));
  66. const float24* src2_ = LookupSourceRegister(instr.common.GetSrc2(is_inverted) + ( is_inverted * address_offset));
  67. const bool negate_src1 = ((bool)swizzle.negate_src1 != false);
  68. const bool negate_src2 = ((bool)swizzle.negate_src2 != false);
  69. float24 src1[4] = {
  70. src1_[(int)swizzle.GetSelectorSrc1(0)],
  71. src1_[(int)swizzle.GetSelectorSrc1(1)],
  72. src1_[(int)swizzle.GetSelectorSrc1(2)],
  73. src1_[(int)swizzle.GetSelectorSrc1(3)],
  74. };
  75. if (negate_src1) {
  76. src1[0] = src1[0] * float24::FromFloat32(-1);
  77. src1[1] = src1[1] * float24::FromFloat32(-1);
  78. src1[2] = src1[2] * float24::FromFloat32(-1);
  79. src1[3] = src1[3] * float24::FromFloat32(-1);
  80. }
  81. float24 src2[4] = {
  82. src2_[(int)swizzle.GetSelectorSrc2(0)],
  83. src2_[(int)swizzle.GetSelectorSrc2(1)],
  84. src2_[(int)swizzle.GetSelectorSrc2(2)],
  85. src2_[(int)swizzle.GetSelectorSrc2(3)],
  86. };
  87. if (negate_src2) {
  88. src2[0] = src2[0] * float24::FromFloat32(-1);
  89. src2[1] = src2[1] * float24::FromFloat32(-1);
  90. src2[2] = src2[2] * float24::FromFloat32(-1);
  91. src2[3] = src2[3] * float24::FromFloat32(-1);
  92. }
  93. float24* dest = (instr.common.dest.Value() < 0x10) ? &state.registers.output[instr.common.dest.Value().GetIndex()][0]
  94. : (instr.common.dest.Value() < 0x20) ? &state.registers.temporary[instr.common.dest.Value().GetIndex()][0]
  95. : dummy_vec4_float24;
  96. state.debug.max_opdesc_id = std::max<u32>(state.debug.max_opdesc_id, 1+instr.common.operand_desc_id);
  97. switch (instr.opcode.Value().EffectiveOpCode()) {
  98. case OpCode::Id::ADD:
  99. {
  100. for (int i = 0; i < 4; ++i) {
  101. if (!swizzle.DestComponentEnabled(i))
  102. continue;
  103. dest[i] = src1[i] + src2[i];
  104. }
  105. break;
  106. }
  107. case OpCode::Id::MUL:
  108. {
  109. for (int i = 0; i < 4; ++i) {
  110. if (!swizzle.DestComponentEnabled(i))
  111. continue;
  112. dest[i] = src1[i] * src2[i];
  113. }
  114. break;
  115. }
  116. case OpCode::Id::FLR:
  117. for (int i = 0; i < 4; ++i) {
  118. if (!swizzle.DestComponentEnabled(i))
  119. continue;
  120. dest[i] = float24::FromFloat32(std::floor(src1[i].ToFloat32()));
  121. }
  122. break;
  123. case OpCode::Id::MAX:
  124. for (int i = 0; i < 4; ++i) {
  125. if (!swizzle.DestComponentEnabled(i))
  126. continue;
  127. dest[i] = std::max(src1[i], src2[i]);
  128. }
  129. break;
  130. case OpCode::Id::MIN:
  131. for (int i = 0; i < 4; ++i) {
  132. if (!swizzle.DestComponentEnabled(i))
  133. continue;
  134. dest[i] = std::min(src1[i], src2[i]);
  135. }
  136. break;
  137. case OpCode::Id::DP3:
  138. case OpCode::Id::DP4:
  139. {
  140. float24 dot = float24::FromFloat32(0.f);
  141. int num_components = (instr.opcode.Value() == OpCode::Id::DP3) ? 3 : 4;
  142. for (int i = 0; i < num_components; ++i)
  143. dot = dot + src1[i] * src2[i];
  144. for (int i = 0; i < 4; ++i) {
  145. if (!swizzle.DestComponentEnabled(i))
  146. continue;
  147. dest[i] = dot;
  148. }
  149. break;
  150. }
  151. // Reciprocal
  152. case OpCode::Id::RCP:
  153. {
  154. for (int i = 0; i < 4; ++i) {
  155. if (!swizzle.DestComponentEnabled(i))
  156. continue;
  157. // TODO: Be stable against division by zero!
  158. // TODO: I think this might be wrong... we should only use one component here
  159. dest[i] = float24::FromFloat32(1.0f / src1[i].ToFloat32());
  160. }
  161. break;
  162. }
  163. // Reciprocal Square Root
  164. case OpCode::Id::RSQ:
  165. {
  166. for (int i = 0; i < 4; ++i) {
  167. if (!swizzle.DestComponentEnabled(i))
  168. continue;
  169. // TODO: Be stable against division by zero!
  170. // TODO: I think this might be wrong... we should only use one component here
  171. dest[i] = float24::FromFloat32(1.0f / sqrt(src1[i].ToFloat32()));
  172. }
  173. break;
  174. }
  175. case OpCode::Id::MOVA:
  176. {
  177. for (int i = 0; i < 2; ++i) {
  178. if (!swizzle.DestComponentEnabled(i))
  179. continue;
  180. // TODO: Figure out how the rounding is done on hardware
  181. state.address_registers[i] = static_cast<s32>(src1[i].ToFloat32());
  182. }
  183. break;
  184. }
  185. case OpCode::Id::MOV:
  186. {
  187. for (int i = 0; i < 4; ++i) {
  188. if (!swizzle.DestComponentEnabled(i))
  189. continue;
  190. dest[i] = src1[i];
  191. }
  192. break;
  193. }
  194. case OpCode::Id::SLT:
  195. case OpCode::Id::SLTI:
  196. for (int i = 0; i < 4; ++i) {
  197. if (!swizzle.DestComponentEnabled(i))
  198. continue;
  199. dest[i] = (src1[i] < src2[i]) ? float24::FromFloat32(1.0f) : float24::FromFloat32(0.0f);
  200. }
  201. break;
  202. case OpCode::Id::CMP:
  203. for (int i = 0; i < 2; ++i) {
  204. // TODO: Can you restrict to one compare via dest masking?
  205. auto compare_op = instr.common.compare_op;
  206. auto op = (i == 0) ? compare_op.x.Value() : compare_op.y.Value();
  207. switch (op) {
  208. case compare_op.Equal:
  209. state.conditional_code[i] = (src1[i] == src2[i]);
  210. break;
  211. case compare_op.NotEqual:
  212. state.conditional_code[i] = (src1[i] != src2[i]);
  213. break;
  214. case compare_op.LessThan:
  215. state.conditional_code[i] = (src1[i] < src2[i]);
  216. break;
  217. case compare_op.LessEqual:
  218. state.conditional_code[i] = (src1[i] <= src2[i]);
  219. break;
  220. case compare_op.GreaterThan:
  221. state.conditional_code[i] = (src1[i] > src2[i]);
  222. break;
  223. case compare_op.GreaterEqual:
  224. state.conditional_code[i] = (src1[i] >= src2[i]);
  225. break;
  226. default:
  227. LOG_ERROR(HW_GPU, "Unknown compare mode %x", static_cast<int>(op));
  228. break;
  229. }
  230. }
  231. break;
  232. default:
  233. LOG_ERROR(HW_GPU, "Unhandled arithmetic instruction: 0x%02x (%s): 0x%08x",
  234. (int)instr.opcode.Value().EffectiveOpCode(), instr.opcode.Value().GetInfo().name, instr.hex);
  235. DEBUG_ASSERT(false);
  236. break;
  237. }
  238. break;
  239. }
  240. case OpCode::Type::MultiplyAdd:
  241. {
  242. if ((instr.opcode.Value().EffectiveOpCode() == OpCode::Id::MAD) ||
  243. (instr.opcode.Value().EffectiveOpCode() == OpCode::Id::MADI)) {
  244. const SwizzlePattern& swizzle = *(SwizzlePattern*)&swizzle_data[instr.mad.operand_desc_id];
  245. bool is_inverted = (instr.opcode.Value().EffectiveOpCode() == OpCode::Id::MADI);
  246. const float24* src1_ = LookupSourceRegister(instr.mad.GetSrc1(is_inverted));
  247. const float24* src2_ = LookupSourceRegister(instr.mad.GetSrc2(is_inverted));
  248. const float24* src3_ = LookupSourceRegister(instr.mad.GetSrc3(is_inverted));
  249. const bool negate_src1 = ((bool)swizzle.negate_src1 != false);
  250. const bool negate_src2 = ((bool)swizzle.negate_src2 != false);
  251. const bool negate_src3 = ((bool)swizzle.negate_src3 != false);
  252. float24 src1[4] = {
  253. src1_[(int)swizzle.GetSelectorSrc1(0)],
  254. src1_[(int)swizzle.GetSelectorSrc1(1)],
  255. src1_[(int)swizzle.GetSelectorSrc1(2)],
  256. src1_[(int)swizzle.GetSelectorSrc1(3)],
  257. };
  258. if (negate_src1) {
  259. src1[0] = src1[0] * float24::FromFloat32(-1);
  260. src1[1] = src1[1] * float24::FromFloat32(-1);
  261. src1[2] = src1[2] * float24::FromFloat32(-1);
  262. src1[3] = src1[3] * float24::FromFloat32(-1);
  263. }
  264. float24 src2[4] = {
  265. src2_[(int)swizzle.GetSelectorSrc2(0)],
  266. src2_[(int)swizzle.GetSelectorSrc2(1)],
  267. src2_[(int)swizzle.GetSelectorSrc2(2)],
  268. src2_[(int)swizzle.GetSelectorSrc2(3)],
  269. };
  270. if (negate_src2) {
  271. src2[0] = src2[0] * float24::FromFloat32(-1);
  272. src2[1] = src2[1] * float24::FromFloat32(-1);
  273. src2[2] = src2[2] * float24::FromFloat32(-1);
  274. src2[3] = src2[3] * float24::FromFloat32(-1);
  275. }
  276. float24 src3[4] = {
  277. src3_[(int)swizzle.GetSelectorSrc3(0)],
  278. src3_[(int)swizzle.GetSelectorSrc3(1)],
  279. src3_[(int)swizzle.GetSelectorSrc3(2)],
  280. src3_[(int)swizzle.GetSelectorSrc3(3)],
  281. };
  282. if (negate_src3) {
  283. src3[0] = src3[0] * float24::FromFloat32(-1);
  284. src3[1] = src3[1] * float24::FromFloat32(-1);
  285. src3[2] = src3[2] * float24::FromFloat32(-1);
  286. src3[3] = src3[3] * float24::FromFloat32(-1);
  287. }
  288. float24* dest = (instr.mad.dest.Value() < 0x10) ? &state.registers.output[instr.mad.dest.Value().GetIndex()][0]
  289. : (instr.mad.dest.Value() < 0x20) ? &state.registers.temporary[instr.mad.dest.Value().GetIndex()][0]
  290. : dummy_vec4_float24;
  291. for (int i = 0; i < 4; ++i) {
  292. if (!swizzle.DestComponentEnabled(i))
  293. continue;
  294. dest[i] = src1[i] * src2[i] + src3[i];
  295. }
  296. } else {
  297. LOG_ERROR(HW_GPU, "Unhandled multiply-add instruction: 0x%02x (%s): 0x%08x",
  298. (int)instr.opcode.Value().EffectiveOpCode(), instr.opcode.Value().GetInfo().name, instr.hex);
  299. }
  300. break;
  301. }
  302. default:
  303. {
  304. static auto evaluate_condition = [](const UnitState& state, bool refx, bool refy, Instruction::FlowControlType flow_control) {
  305. bool results[2] = { refx == state.conditional_code[0],
  306. refy == state.conditional_code[1] };
  307. switch (flow_control.op) {
  308. case flow_control.Or:
  309. return results[0] || results[1];
  310. case flow_control.And:
  311. return results[0] && results[1];
  312. case flow_control.JustX:
  313. return results[0];
  314. case flow_control.JustY:
  315. return results[1];
  316. }
  317. };
  318. // Handle each instruction on its own
  319. switch (instr.opcode.Value()) {
  320. case OpCode::Id::END:
  321. exit_loop = true;
  322. break;
  323. case OpCode::Id::JMPC:
  324. if (evaluate_condition(state, instr.flow_control.refx, instr.flow_control.refy, instr.flow_control)) {
  325. state.program_counter = instr.flow_control.dest_offset - 1;
  326. }
  327. break;
  328. case OpCode::Id::JMPU:
  329. if (uniforms.b[instr.flow_control.bool_uniform_id]) {
  330. state.program_counter = instr.flow_control.dest_offset - 1;
  331. }
  332. break;
  333. case OpCode::Id::CALL:
  334. call(state,
  335. instr.flow_control.dest_offset,
  336. instr.flow_control.num_instructions,
  337. state.program_counter + 1, 0, 0);
  338. break;
  339. case OpCode::Id::CALLU:
  340. if (uniforms.b[instr.flow_control.bool_uniform_id]) {
  341. call(state,
  342. instr.flow_control.dest_offset,
  343. instr.flow_control.num_instructions,
  344. state.program_counter + 1, 0, 0);
  345. }
  346. break;
  347. case OpCode::Id::CALLC:
  348. if (evaluate_condition(state, instr.flow_control.refx, instr.flow_control.refy, instr.flow_control)) {
  349. call(state,
  350. instr.flow_control.dest_offset,
  351. instr.flow_control.num_instructions,
  352. state.program_counter + 1, 0, 0);
  353. }
  354. break;
  355. case OpCode::Id::NOP:
  356. break;
  357. case OpCode::Id::IFU:
  358. if (uniforms.b[instr.flow_control.bool_uniform_id]) {
  359. call(state,
  360. state.program_counter + 1,
  361. instr.flow_control.dest_offset - state.program_counter - 1,
  362. instr.flow_control.dest_offset + instr.flow_control.num_instructions, 0, 0);
  363. } else {
  364. call(state,
  365. instr.flow_control.dest_offset,
  366. instr.flow_control.num_instructions,
  367. instr.flow_control.dest_offset + instr.flow_control.num_instructions, 0, 0);
  368. }
  369. break;
  370. case OpCode::Id::IFC:
  371. {
  372. // TODO: Do we need to consider swizzlers here?
  373. if (evaluate_condition(state, instr.flow_control.refx, instr.flow_control.refy, instr.flow_control)) {
  374. call(state,
  375. state.program_counter + 1,
  376. instr.flow_control.dest_offset - state.program_counter - 1,
  377. instr.flow_control.dest_offset + instr.flow_control.num_instructions, 0, 0);
  378. } else {
  379. call(state,
  380. instr.flow_control.dest_offset,
  381. instr.flow_control.num_instructions,
  382. instr.flow_control.dest_offset + instr.flow_control.num_instructions, 0, 0);
  383. }
  384. break;
  385. }
  386. case OpCode::Id::LOOP:
  387. {
  388. state.address_registers[2] = uniforms.i[instr.flow_control.int_uniform_id].y;
  389. call(state,
  390. state.program_counter + 1,
  391. instr.flow_control.dest_offset - state.program_counter + 1,
  392. instr.flow_control.dest_offset + 1,
  393. uniforms.i[instr.flow_control.int_uniform_id].x,
  394. uniforms.i[instr.flow_control.int_uniform_id].z);
  395. break;
  396. }
  397. default:
  398. LOG_ERROR(HW_GPU, "Unhandled instruction: 0x%02x (%s): 0x%08x",
  399. (int)instr.opcode.Value().EffectiveOpCode(), instr.opcode.Value().GetInfo().name, instr.hex);
  400. break;
  401. }
  402. break;
  403. }
  404. }
  405. ++state.program_counter;
  406. if (exit_loop)
  407. break;
  408. }
  409. }
  410. } // namespace
  411. } // namespace