memory.h 5.5 KB

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  1. // Copyright 2014 Citra Emulator Project
  2. // Licensed under GPLv2 or any later version
  3. // Refer to the license.txt file included.
  4. #pragma once
  5. #include <cstddef>
  6. #include <string>
  7. #include "common/common_types.h"
  8. namespace Memory {
  9. /**
  10. * Page size used by the ARM architecture. This is the smallest granularity with which memory can
  11. * be mapped.
  12. */
  13. const u32 PAGE_SIZE = 0x1000;
  14. const u32 PAGE_MASK = PAGE_SIZE - 1;
  15. const int PAGE_BITS = 12;
  16. /// Physical memory regions as seen from the ARM11
  17. enum : PAddr {
  18. /// IO register area
  19. IO_AREA_PADDR = 0x10100000,
  20. IO_AREA_SIZE = 0x01000000, ///< IO area size (16MB)
  21. IO_AREA_PADDR_END = IO_AREA_PADDR + IO_AREA_SIZE,
  22. /// MPCore internal memory region
  23. MPCORE_RAM_PADDR = 0x17E00000,
  24. MPCORE_RAM_SIZE = 0x00002000, ///< MPCore internal memory size (8KB)
  25. MPCORE_RAM_PADDR_END = MPCORE_RAM_PADDR + MPCORE_RAM_SIZE,
  26. /// Video memory
  27. VRAM_PADDR = 0x18000000,
  28. VRAM_SIZE = 0x00600000, ///< VRAM size (6MB)
  29. VRAM_PADDR_END = VRAM_PADDR + VRAM_SIZE,
  30. /// DSP memory
  31. DSP_RAM_PADDR = 0x1FF00000,
  32. DSP_RAM_SIZE = 0x00080000, ///< DSP memory size (512KB)
  33. DSP_RAM_PADDR_END = DSP_RAM_PADDR + DSP_RAM_SIZE,
  34. /// AXI WRAM
  35. AXI_WRAM_PADDR = 0x1FF80000,
  36. AXI_WRAM_SIZE = 0x00080000, ///< AXI WRAM size (512KB)
  37. AXI_WRAM_PADDR_END = AXI_WRAM_PADDR + AXI_WRAM_SIZE,
  38. /// Main FCRAM
  39. FCRAM_PADDR = 0x20000000,
  40. FCRAM_SIZE = 0x08000000, ///< FCRAM size (128MB)
  41. FCRAM_PADDR_END = FCRAM_PADDR + FCRAM_SIZE,
  42. };
  43. /// Virtual user-space memory regions
  44. enum : VAddr {
  45. /// Where the application text, data and bss reside.
  46. PROCESS_IMAGE_VADDR = 0x00100000,
  47. PROCESS_IMAGE_MAX_SIZE = 0x03F00000,
  48. PROCESS_IMAGE_VADDR_END = PROCESS_IMAGE_VADDR + PROCESS_IMAGE_MAX_SIZE,
  49. /// Area where IPC buffers are mapped onto.
  50. IPC_MAPPING_VADDR = 0x04000000,
  51. IPC_MAPPING_SIZE = 0x04000000,
  52. IPC_MAPPING_VADDR_END = IPC_MAPPING_VADDR + IPC_MAPPING_SIZE,
  53. /// Application heap (includes stack).
  54. HEAP_VADDR = 0x08000000,
  55. HEAP_SIZE = 0x08000000,
  56. HEAP_VADDR_END = HEAP_VADDR + HEAP_SIZE,
  57. /// Area where shared memory buffers are mapped onto.
  58. SHARED_MEMORY_VADDR = 0x10000000,
  59. SHARED_MEMORY_SIZE = 0x04000000,
  60. SHARED_MEMORY_VADDR_END = SHARED_MEMORY_VADDR + SHARED_MEMORY_SIZE,
  61. /// Maps 1:1 to an offset in FCRAM. Used for HW allocations that need to be linear in physical memory.
  62. LINEAR_HEAP_VADDR = 0x14000000,
  63. LINEAR_HEAP_SIZE = 0x08000000,
  64. LINEAR_HEAP_VADDR_END = LINEAR_HEAP_VADDR + LINEAR_HEAP_SIZE,
  65. /// Maps 1:1 to the IO register area.
  66. IO_AREA_VADDR = 0x1EC00000,
  67. IO_AREA_VADDR_END = IO_AREA_VADDR + IO_AREA_SIZE,
  68. /// Maps 1:1 to VRAM.
  69. VRAM_VADDR = 0x1F000000,
  70. VRAM_VADDR_END = VRAM_VADDR + VRAM_SIZE,
  71. /// Maps 1:1 to DSP memory.
  72. DSP_RAM_VADDR = 0x1FF00000,
  73. DSP_RAM_VADDR_END = DSP_RAM_VADDR + DSP_RAM_SIZE,
  74. /// Read-only page containing kernel and system configuration values.
  75. CONFIG_MEMORY_VADDR = 0x1FF80000,
  76. CONFIG_MEMORY_SIZE = 0x00001000,
  77. CONFIG_MEMORY_VADDR_END = CONFIG_MEMORY_VADDR + CONFIG_MEMORY_SIZE,
  78. /// Usually read-only page containing mostly values read from hardware.
  79. SHARED_PAGE_VADDR = 0x1FF81000,
  80. SHARED_PAGE_SIZE = 0x00001000,
  81. SHARED_PAGE_VADDR_END = SHARED_PAGE_VADDR + SHARED_PAGE_SIZE,
  82. /// Area where TLS (Thread-Local Storage) buffers are allocated.
  83. TLS_AREA_VADDR = 0x1FF82000,
  84. TLS_ENTRY_SIZE = 0x200,
  85. /// Equivalent to LINEAR_HEAP_VADDR, but expanded to cover the extra memory in the New 3DS.
  86. NEW_LINEAR_HEAP_VADDR = 0x30000000,
  87. NEW_LINEAR_HEAP_SIZE = 0x10000000,
  88. NEW_LINEAR_HEAP_VADDR_END = NEW_LINEAR_HEAP_VADDR + NEW_LINEAR_HEAP_SIZE,
  89. };
  90. bool IsValidVirtualAddress(const VAddr addr);
  91. bool IsValidPhysicalAddress(const PAddr addr);
  92. u8 Read8(VAddr addr);
  93. u16 Read16(VAddr addr);
  94. u32 Read32(VAddr addr);
  95. u64 Read64(VAddr addr);
  96. void Write8(VAddr addr, u8 data);
  97. void Write16(VAddr addr, u16 data);
  98. void Write32(VAddr addr, u32 data);
  99. void Write64(VAddr addr, u64 data);
  100. void ReadBlock(const VAddr src_addr, void* dest_buffer, size_t size);
  101. void WriteBlock(const VAddr dest_addr, const void* src_buffer, size_t size);
  102. void ZeroBlock(const VAddr dest_addr, const size_t size);
  103. void CopyBlock(VAddr dest_addr, VAddr src_addr, size_t size);
  104. u8* GetPointer(VAddr virtual_address);
  105. std::string ReadCString(VAddr virtual_address, std::size_t max_length);
  106. /**
  107. * Converts a virtual address inside a region with 1:1 mapping to physical memory to a physical
  108. * address. This should be used by services to translate addresses for use by the hardware.
  109. */
  110. PAddr VirtualToPhysicalAddress(VAddr addr);
  111. /**
  112. * Undoes a mapping performed by VirtualToPhysicalAddress().
  113. */
  114. VAddr PhysicalToVirtualAddress(PAddr addr);
  115. /**
  116. * Gets a pointer to the memory region beginning at the specified physical address.
  117. *
  118. * @note This is currently implemented using PhysicalToVirtualAddress().
  119. */
  120. u8* GetPhysicalPointer(PAddr address);
  121. /**
  122. * Adds the supplied value to the rasterizer resource cache counter of each
  123. * page touching the region.
  124. */
  125. void RasterizerMarkRegionCached(PAddr start, u32 size, int count_delta);
  126. /**
  127. * Flushes any externally cached rasterizer resources touching the given region.
  128. */
  129. void RasterizerFlushRegion(PAddr start, u32 size);
  130. /**
  131. * Flushes and invalidates any externally cached rasterizer resources touching the given region.
  132. */
  133. void RasterizerFlushAndInvalidateRegion(PAddr start, u32 size);
  134. }