vfp.cpp 4.6 KB

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  1. /*
  2. armvfp.c - ARM VFPv3 emulation unit
  3. Copyright (C) 2003 Skyeye Develop Group
  4. for help please send mail to <skyeye-developer@lists.gro.clinux.org>
  5. This program is free software; you can redistribute it and/or modify
  6. it under the terms of the GNU General Public License as published by
  7. the Free Software Foundation; either version 2 of the License, or
  8. (at your option) any later version.
  9. This program is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. GNU General Public License for more details.
  13. You should have received a copy of the GNU General Public License
  14. along with this program; if not, write to the Free Software
  15. Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  16. */
  17. /* Note: this file handles interface with arm core and vfp registers */
  18. #include "common/common_funcs.h"
  19. #include "common/logging/log.h"
  20. #include "core/arm/skyeye_common/armdefs.h"
  21. #include "core/arm/skyeye_common/vfp/asm_vfp.h"
  22. #include "core/arm/skyeye_common/vfp/vfp.h"
  23. void VFPInit(ARMul_State* state)
  24. {
  25. state->VFP[VFP_FPSID] = VFP_FPSID_IMPLMEN<<24 | VFP_FPSID_SW<<23 | VFP_FPSID_SUBARCH<<16 |
  26. VFP_FPSID_PARTNUM<<8 | VFP_FPSID_VARIANT<<4 | VFP_FPSID_REVISION;
  27. state->VFP[VFP_FPEXC] = 0;
  28. state->VFP[VFP_FPSCR] = 0;
  29. // ARM11 MPCore instruction register reset values.
  30. state->VFP[VFP_FPINST] = 0xEE000A00;
  31. state->VFP[VFP_FPINST2] = 0;
  32. // ARM11 MPCore feature register values.
  33. state->VFP[VFP_MVFR0] = 0x11111111;
  34. state->VFP[VFP_MVFR1] = 0;
  35. }
  36. void VMOVBRS(ARMul_State* state, u32 to_arm, u32 t, u32 n, u32* value)
  37. {
  38. if (to_arm)
  39. {
  40. *value = state->ExtReg[n];
  41. }
  42. else
  43. {
  44. state->ExtReg[n] = *value;
  45. }
  46. }
  47. void VMOVBRRD(ARMul_State* state, u32 to_arm, u32 t, u32 t2, u32 n, u32* value1, u32* value2)
  48. {
  49. if (to_arm)
  50. {
  51. *value2 = state->ExtReg[n*2+1];
  52. *value1 = state->ExtReg[n*2];
  53. }
  54. else
  55. {
  56. state->ExtReg[n*2+1] = *value2;
  57. state->ExtReg[n*2] = *value1;
  58. }
  59. }
  60. void VMOVBRRSS(ARMul_State* state, u32 to_arm, u32 t, u32 t2, u32 n, u32* value1, u32* value2)
  61. {
  62. if (to_arm)
  63. {
  64. *value1 = state->ExtReg[n+0];
  65. *value2 = state->ExtReg[n+1];
  66. }
  67. else
  68. {
  69. state->ExtReg[n+0] = *value1;
  70. state->ExtReg[n+1] = *value2;
  71. }
  72. }
  73. void VMOVI(ARMul_State* state, u32 single, u32 d, u32 imm)
  74. {
  75. if (single)
  76. {
  77. state->ExtReg[d] = imm;
  78. }
  79. else
  80. {
  81. /* Check endian please */
  82. state->ExtReg[d*2+1] = imm;
  83. state->ExtReg[d*2] = 0;
  84. }
  85. }
  86. void VMOVR(ARMul_State* state, u32 single, u32 d, u32 m)
  87. {
  88. if (single)
  89. {
  90. state->ExtReg[d] = state->ExtReg[m];
  91. }
  92. else
  93. {
  94. /* Check endian please */
  95. state->ExtReg[d*2+1] = state->ExtReg[m*2+1];
  96. state->ExtReg[d*2] = state->ExtReg[m*2];
  97. }
  98. }
  99. /* Miscellaneous functions */
  100. int32_t vfp_get_float(ARMul_State* state, unsigned int reg)
  101. {
  102. LOG_TRACE(Core_ARM11, "VFP get float: s%d=[%08x]\n", reg, state->ExtReg[reg]);
  103. return state->ExtReg[reg];
  104. }
  105. void vfp_put_float(ARMul_State* state, int32_t val, unsigned int reg)
  106. {
  107. LOG_TRACE(Core_ARM11, "VFP put float: s%d <= [%08x]\n", reg, val);
  108. state->ExtReg[reg] = val;
  109. }
  110. uint64_t vfp_get_double(ARMul_State* state, unsigned int reg)
  111. {
  112. uint64_t result = ((uint64_t) state->ExtReg[reg*2+1])<<32 | state->ExtReg[reg*2];
  113. LOG_TRACE(Core_ARM11, "VFP get double: s[%d-%d]=[%016llx]\n", reg * 2 + 1, reg * 2, result);
  114. return result;
  115. }
  116. void vfp_put_double(ARMul_State* state, uint64_t val, unsigned int reg)
  117. {
  118. LOG_TRACE(Core_ARM11, "VFP put double: s[%d-%d] <= [%08x-%08x]\n", reg * 2 + 1, reg * 2, (uint32_t)(val >> 32), (uint32_t)(val & 0xffffffff));
  119. state->ExtReg[reg*2] = (uint32_t) (val & 0xffffffff);
  120. state->ExtReg[reg*2+1] = (uint32_t) (val>>32);
  121. }
  122. /*
  123. * Process bitmask of exception conditions. (from vfpmodule.c)
  124. */
  125. void vfp_raise_exceptions(ARMul_State* state, u32 exceptions, u32 inst, u32 fpscr)
  126. {
  127. LOG_TRACE(Core_ARM11, "VFP: raising exceptions %08x\n", exceptions);
  128. if (exceptions == VFP_EXCEPTION_ERROR) {
  129. LOG_CRITICAL(Core_ARM11, "unhandled bounce %x\n", inst);
  130. Crash();
  131. }
  132. /*
  133. * If any of the status flags are set, update the FPSCR.
  134. * Comparison instructions always return at least one of
  135. * these flags set.
  136. */
  137. if (exceptions & (FPSCR_NFLAG|FPSCR_ZFLAG|FPSCR_CFLAG|FPSCR_VFLAG))
  138. fpscr &= ~(FPSCR_NFLAG|FPSCR_ZFLAG|FPSCR_CFLAG|FPSCR_VFLAG);
  139. fpscr |= exceptions;
  140. state->VFP[VFP_FPSCR] = fpscr;
  141. }