cdma_pusher.h 3.0 KB

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  1. // SPDX-FileCopyrightText: Copyright 2020 yuzu Emulator Project
  2. // SPDX-License-Identifier: GPL-2.0-or-later
  3. #pragma once
  4. #include <memory>
  5. #include <vector>
  6. #include "common/bit_field.h"
  7. #include "common/common_funcs.h"
  8. #include "common/common_types.h"
  9. namespace Tegra {
  10. namespace Host1x {
  11. class Control;
  12. class Host1x;
  13. class Nvdec;
  14. class SyncptIncrManager;
  15. class Vic;
  16. } // namespace Host1x
  17. enum class ChSubmissionMode : u32 {
  18. SetClass = 0,
  19. Incrementing = 1,
  20. NonIncrementing = 2,
  21. Mask = 3,
  22. Immediate = 4,
  23. Restart = 5,
  24. Gather = 6,
  25. };
  26. enum class ChClassId : u32 {
  27. NoClass = 0x0,
  28. Control = 0x1,
  29. VideoEncodeMpeg = 0x20,
  30. VideoEncodeNvEnc = 0x21,
  31. VideoStreamingVi = 0x30,
  32. VideoStreamingIsp = 0x32,
  33. VideoStreamingIspB = 0x34,
  34. VideoStreamingViI2c = 0x36,
  35. GraphicsVic = 0x5d,
  36. Graphics3D = 0x60,
  37. GraphicsGpu = 0x61,
  38. Tsec = 0xe0,
  39. TsecB = 0xe1,
  40. NvJpg = 0xc0,
  41. NvDec = 0xf0
  42. };
  43. union ChCommandHeader {
  44. u32 raw;
  45. BitField<0, 16, u32> value;
  46. BitField<16, 12, u32> method_offset;
  47. BitField<28, 4, ChSubmissionMode> submission_mode;
  48. };
  49. static_assert(sizeof(ChCommandHeader) == sizeof(u32), "ChCommand header is an invalid size");
  50. struct ChCommand {
  51. ChClassId class_id{};
  52. int method_offset{};
  53. std::vector<u32> arguments;
  54. };
  55. using ChCommandHeaderList = std::vector<ChCommandHeader>;
  56. using ChCommandList = std::vector<ChCommand>;
  57. struct ThiRegisters {
  58. u32_le increment_syncpt{};
  59. INSERT_PADDING_WORDS(1);
  60. u32_le increment_syncpt_error{};
  61. u32_le ctx_switch_incremement_syncpt{};
  62. INSERT_PADDING_WORDS(4);
  63. u32_le ctx_switch{};
  64. INSERT_PADDING_WORDS(1);
  65. u32_le ctx_syncpt_eof{};
  66. INSERT_PADDING_WORDS(5);
  67. u32_le method_0{};
  68. u32_le method_1{};
  69. INSERT_PADDING_WORDS(12);
  70. u32_le int_status{};
  71. u32_le int_mask{};
  72. };
  73. enum class ThiMethod : u32 {
  74. IncSyncpt = offsetof(ThiRegisters, increment_syncpt) / sizeof(u32),
  75. SetMethod0 = offsetof(ThiRegisters, method_0) / sizeof(u32),
  76. SetMethod1 = offsetof(ThiRegisters, method_1) / sizeof(u32),
  77. };
  78. class CDmaPusher {
  79. public:
  80. explicit CDmaPusher(Host1x::Host1x& host1x);
  81. ~CDmaPusher();
  82. /// Process the command entry
  83. void ProcessEntries(ChCommandHeaderList&& entries);
  84. private:
  85. /// Invoke command class devices to execute the command based on the current state
  86. void ExecuteCommand(u32 state_offset, u32 data);
  87. /// Write arguments value to the ThiRegisters member at the specified offset
  88. void ThiStateWrite(ThiRegisters& state, u32 offset, u32 argument);
  89. Host1x::Host1x& host1x;
  90. std::shared_ptr<Tegra::Host1x::Nvdec> nvdec_processor;
  91. std::unique_ptr<Tegra::Host1x::Vic> vic_processor;
  92. std::unique_ptr<Tegra::Host1x::Control> host1x_processor;
  93. std::unique_ptr<Host1x::SyncptIncrManager> sync_manager;
  94. ChClassId current_class{};
  95. ThiRegisters vic_thi_state{};
  96. ThiRegisters nvdec_thi_state{};
  97. u32 count{};
  98. u32 offset{};
  99. u32 mask{};
  100. bool incrementing{};
  101. };
  102. } // namespace Tegra