GPU: Added a command processor to decode the GPU pushbuffers and forward the commands to their respective engines.

src/core/hle/service/nvdrv/devices/nvhost_as_gpu.h

@@ -21,7 +21,7 @@ class nvmap;
 class nvhost_as_gpu final : public nvdevice {
 public:
     nvhost_as_gpu(std::shared_ptr<nvmap> nvmap_dev, std::shared_ptr<MemoryManager> memory_manager)
-        : nvdevice(), nvmap_dev(std::move(nvmap_dev)), memory_manager(std::move(memory_manager)) {}
+        : nvmap_dev(std::move(nvmap_dev)), memory_manager(std::move(memory_manager)) {}
     ~nvhost_as_gpu() override = default;
 
     u32 ioctl(Ioctl command, const std::vector<u8>& input, std::vector<u8>& output) override;

src/core/hle/service/nvdrv/devices/nvhost_gpu.cpp

@@ -6,6 +6,7 @@
 #include "common/assert.h"
 #include "common/logging/log.h"
 #include "core/hle/service/nvdrv/devices/nvhost_gpu.h"
+#include "video_core/command_processor.h"
 
 namespace Service {
 namespace Nvidia {
@@ -130,7 +131,8 @@ u32 nvhost_gpu::SubmitGPFIFO(const std::vector<u8>& input, std::vector<u8>& outp
     std::memcpy(&entries[0], &input.data()[sizeof(IoctlSubmitGpfifo)],
                 params.num_entries * sizeof(IoctlGpfifoEntry));
     for (auto entry : entries) {
-        VAddr va_addr = entry.Address();
+        VAddr va_addr = memory_manager->PhysicalToVirtualAddress(entry.Address());
+        Tegra::CommandProcessor::ProcessCommandList(va_addr, entry.sz);
         // TODO(ogniK): Process these
     }
     params.fence_out.id = 0;

src/core/hle/service/nvdrv/devices/nvhost_gpu.h

@@ -22,7 +22,7 @@ constexpr u32 NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO(0x8);
 class nvhost_gpu final : public nvdevice {
 public:
     nvhost_gpu(std::shared_ptr<nvmap> nvmap_dev, std::shared_ptr<MemoryManager> memory_manager)
-        : nvdevice(), nvmap_dev(std::move(nvmap_dev)), memory_manager(std::move(memory_manager)) {}
+        : nvmap_dev(std::move(nvmap_dev)), memory_manager(std::move(memory_manager)) {}
     ~nvhost_gpu() override = default;
 
     u32 ioctl(Ioctl command, const std::vector<u8>& input, std::vector<u8>& output) override;

src/video_core/CMakeLists.txt

@@ -1,4 +1,12 @@
 add_library(video_core STATIC
+    command_processor.cpp
+    command_processor.h
+    engines/fermi_2d.cpp
+    engines/fermi_2d.h
+    engines/maxwell_3d.cpp
+    engines/maxwell_3d.h
+    engines/maxwell_compute.cpp
+    engines/maxwell_compute.h
     renderer_base.cpp
     renderer_base.h
     renderer_opengl/gl_resource_manager.h

src/video_core/command_processor.cpp

@@ -0,0 +1,130 @@
+// Copyright 2018 yuzu Emulator Project
+// Licensed under GPLv2 or any later version
+// Refer to the license.txt file included.
+
+#include <array>
+#include <cstddef>
+#include <memory>
+#include <utility>
+#include "common/assert.h"
+#include "common/logging/log.h"
+#include "common/microprofile.h"
+#include "common/vector_math.h"
+#include "core/memory.h"
+#include "core/tracer/recorder.h"
+#include "video_core/command_processor.h"
+#include "video_core/engines/fermi_2d.h"
+#include "video_core/engines/maxwell_3d.h"
+#include "video_core/engines/maxwell_compute.h"
+#include "video_core/renderer_base.h"
+#include "video_core/video_core.h"
+
+namespace Tegra {
+
+namespace CommandProcessor {
+
+enum class BufferMethods {
+    BindObject = 0,
+    CountBufferMethods = 0x100,
+};
+
+enum class EngineID {
+    FERMI_TWOD_A = 0x902D, // 2D Engine
+    MAXWELL_B = 0xB197,    // 3D Engine
+    MAXWELL_COMPUTE_B = 0xB1C0,
+    KEPLER_INLINE_TO_MEMORY_B = 0xA140,
+    MAXWELL_DMA_COPY_A = 0xB0B5,
+};
+
+// Mapping of subchannels to their bound engine ids.
+static std::unordered_map<u32, EngineID> bound_engines;
+
+static void WriteReg(u32 method, u32 subchannel, u32 value) {
+    LOG_WARNING(HW_GPU, "Processing method %08X on subchannel %u value %08X", method, subchannel,
+                value);
+
+    if (method == static_cast<u32>(BufferMethods::BindObject)) {
+        // Bind the current subchannel to the desired engine id.
+        LOG_DEBUG(HW_GPU, "Binding subchannel %u to engine %u", subchannel, value);
+        ASSERT(bound_engines.find(subchannel) == bound_engines.end());
+        bound_engines[subchannel] = static_cast<EngineID>(value);
+        return;
+    }
+
+    if (method < static_cast<u32>(BufferMethods::CountBufferMethods)) {
+        // TODO(Subv): Research and implement these methods.
+        LOG_ERROR(HW_GPU, "Special buffer methods other than Bind are not implemented");
+        return;
+    }
+
+    ASSERT(bound_engines.find(subchannel) != bound_engines.end());
+
+    const EngineID engine = bound_engines[subchannel];
+
+    switch (engine) {
+    case EngineID::FERMI_TWOD_A:
+        Engines::Fermi2D::WriteReg(method, value);
+        break;
+    case EngineID::MAXWELL_B:
+        Engines::Maxwell3D::WriteReg(method, value);
+        break;
+    case EngineID::MAXWELL_COMPUTE_B:
+        Engines::MaxwellCompute::WriteReg(method, value);
+        break;
+    default:
+        UNIMPLEMENTED();
+    }
+}
+
+void ProcessCommandList(VAddr address, u32 size) {
+    VAddr current_addr = address;
+    while (current_addr < address + size * sizeof(CommandHeader)) {
+        const CommandHeader header = {Memory::Read32(current_addr)};
+        current_addr += sizeof(u32);
+
+        switch (header.mode.Value()) {
+        case SubmissionMode::IncreasingOld:
+        case SubmissionMode::Increasing: {
+            // Increase the method value with each argument.
+            for (unsigned i = 0; i < header.arg_count; ++i) {
+                WriteReg(header.method + i, header.subchannel, Memory::Read32(current_addr));
+                current_addr += sizeof(u32);
+            }
+            break;
+        }
+        case SubmissionMode::NonIncreasingOld:
+        case SubmissionMode::NonIncreasing: {
+            // Use the same method value for all arguments.
+            for (unsigned i = 0; i < header.arg_count; ++i) {
+                WriteReg(header.method, header.subchannel, Memory::Read32(current_addr));
+                current_addr += sizeof(u32);
+            }
+            break;
+        }
+        case SubmissionMode::IncreaseOnce: {
+            ASSERT(header.arg_count.Value() >= 1);
+            // Use the original method for the first argument and then the next method for all other
+            // arguments.
+            WriteReg(header.method, header.subchannel, Memory::Read32(current_addr));
+            current_addr += sizeof(u32);
+            // Use the same method value for all arguments.
+            for (unsigned i = 1; i < header.arg_count; ++i) {
+                WriteReg(header.method + 1, header.subchannel, Memory::Read32(current_addr));
+                current_addr += sizeof(u32);
+            }
+            break;
+        }
+        case SubmissionMode::Inline: {
+            // The register value is stored in the bits 16-28 as an immediate
+            WriteReg(header.method, header.subchannel, header.inline_data);
+            break;
+        }
+        default:
+            UNIMPLEMENTED();
+        }
+    }
+}
+
+} // namespace CommandProcessor
+
+} // namespace Tegra

src/video_core/command_processor.h

@@ -0,0 +1,43 @@
+// Copyright 2018 yuzu Emulator Project
+// Licensed under GPLv2 or any later version
+// Refer to the license.txt file included.
+
+#pragma once
+
+#include <type_traits>
+#include "common/bit_field.h"
+#include "common/common_types.h"
+
+namespace Tegra {
+
+namespace CommandProcessor {
+
+enum class SubmissionMode : u32 {
+    IncreasingOld = 0,
+    Increasing = 1,
+    NonIncreasingOld = 2,
+    NonIncreasing = 3,
+    Inline = 4,
+    IncreaseOnce = 5
+};
+
+union CommandHeader {
+    u32 hex;
+
+    BitField<0, 13, u32> method;
+    BitField<13, 3, u32> subchannel;
+
+    BitField<16, 13, u32> arg_count;
+    BitField<16, 13, u32> inline_data;
+
+    BitField<29, 3, SubmissionMode> mode;
+};
+static_assert(std::is_standard_layout<CommandHeader>::value == true,
+              "CommandHeader does not use standard layout");
+static_assert(sizeof(CommandHeader) == sizeof(u32), "CommandHeader has incorrect size!");
+
+void ProcessCommandList(VAddr address, u32 size);
+
+} // namespace CommandProcessor
+
+} // namespace Tegra

src/video_core/engines/fermi_2d.cpp

@@ -0,0 +1,15 @@
+// Copyright 2018 yuzu Emulator Project
+// Licensed under GPLv2 or any later version
+// Refer to the license.txt file included.
+
+#include "video_core/engines/fermi_2d.h"
+
+namespace Tegra {
+namespace Engines {
+namespace Fermi2D {
+
+void WriteReg(u32 method, u32 value) {}
+
+} // namespace Fermi2D
+} // namespace Engines
+} // namespace Tegra

src/video_core/engines/fermi_2d.h

@@ -0,0 +1,18 @@
+// Copyright 2018 yuzu Emulator Project
+// Licensed under GPLv2 or any later version
+// Refer to the license.txt file included.
+
+#pragma once
+
+#include "common/common_types.h"
+
+namespace Tegra {
+namespace Engines {
+namespace Fermi2D {
+
+void WriteReg(u32 method, u32 value);
+
+} // namespace Fermi2D
+
+} // namespace Engines
+} // namespace Tegra

src/video_core/engines/maxwell_3d.cpp

@@ -0,0 +1,15 @@
+// Copyright 2018 yuzu Emulator Project
+// Licensed under GPLv2 or any later version
+// Refer to the license.txt file included.
+
+#include "video_core/engines/maxwell_3d.h"
+
+namespace Tegra {
+namespace Engines {
+namespace Maxwell3D {
+
+void WriteReg(u32 method, u32 value) {}
+
+} // namespace Maxwell3D
+} // namespace Engines
+} // namespace Tegra

src/video_core/engines/maxwell_3d.h

@@ -0,0 +1,18 @@
+// Copyright 2018 yuzu Emulator Project
+// Licensed under GPLv2 or any later version
+// Refer to the license.txt file included.
+
+#pragma once
+
+#include "common/common_types.h"
+
+namespace Tegra {
+namespace Engines {
+namespace Maxwell3D {
+
+void WriteReg(u32 method, u32 value);
+
+} // namespace Maxwell3D
+
+} // namespace Engines
+} // namespace Tegra

src/video_core/engines/maxwell_compute.cpp

@@ -0,0 +1,15 @@
+// Copyright 2018 yuzu Emulator Project
+// Licensed under GPLv2 or any later version
+// Refer to the license.txt file included.
+
+#include "video_core/engines/maxwell_compute.h"
+
+namespace Tegra {
+namespace Engines {
+namespace MaxwellCompute {
+
+void WriteReg(u32 method, u32 value) {}
+
+} // namespace MaxwellCompute
+} // namespace Engines
+} // namespace Tegra

src/video_core/engines/maxwell_compute.h

@@ -0,0 +1,18 @@
+// Copyright 2018 yuzu Emulator Project
+// Licensed under GPLv2 or any later version
+// Refer to the license.txt file included.
+
+#pragma once
+
+#include "common/common_types.h"
+
+namespace Tegra {
+namespace Engines {
+namespace MaxwellCompute {
+
+void WriteReg(u32 method, u32 value);
+
+} // namespace MaxwellCompute
+
+} // namespace Engines
+} // namespace Tegra