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@@ -66,6 +66,22 @@ public:
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memory.Write64(vaddr + 8, value[1]);
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memory.Write64(vaddr + 8, value[1]);
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}
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}
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+ bool MemoryWriteExclusive8(u64 vaddr, std::uint8_t value, std::uint8_t expected) override {
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+ return parent.system.Memory().WriteExclusive8(vaddr, value, expected);
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+ }
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+ bool MemoryWriteExclusive16(u64 vaddr, std::uint16_t value, std::uint16_t expected) override {
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+ return parent.system.Memory().WriteExclusive16(vaddr, value, expected);
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+ }
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+ bool MemoryWriteExclusive32(u64 vaddr, std::uint32_t value, std::uint32_t expected) override {
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+ return parent.system.Memory().WriteExclusive32(vaddr, value, expected);
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+ }
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+ bool MemoryWriteExclusive64(u64 vaddr, std::uint64_t value, std::uint64_t expected) override {
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+ return parent.system.Memory().WriteExclusive64(vaddr, value, expected);
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+ }
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+ bool MemoryWriteExclusive128(u64 vaddr, Vector value, Vector expected) override {
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+ return parent.system.Memory().WriteExclusive128(vaddr, value, expected);
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+ }
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+
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void InterpreterFallback(u64 pc, std::size_t num_instructions) override {
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void InterpreterFallback(u64 pc, std::size_t num_instructions) override {
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LOG_INFO(Core_ARM, "Unicorn fallback @ 0x{:X} for {} instructions (instr = {:08X})", pc,
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LOG_INFO(Core_ARM, "Unicorn fallback @ 0x{:X} for {} instructions (instr = {:08X})", pc,
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num_instructions, MemoryReadCode(pc));
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num_instructions, MemoryReadCode(pc));
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@@ -284,9 +300,29 @@ DynarmicExclusiveMonitor::DynarmicExclusiveMonitor(Memory::Memory& memory, std::
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DynarmicExclusiveMonitor::~DynarmicExclusiveMonitor() = default;
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DynarmicExclusiveMonitor::~DynarmicExclusiveMonitor() = default;
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-void DynarmicExclusiveMonitor::SetExclusive(std::size_t core_index, VAddr addr) {
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- // Size doesn't actually matter.
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- monitor.Mark(core_index, addr, 16);
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+void DynarmicExclusiveMonitor::SetExclusive8(std::size_t core_index, VAddr addr) {
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+ monitor.Mark<u8>(core_index, addr, 1, [&]() -> u8 { return memory.Read8(addr); });
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+}
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+
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+void DynarmicExclusiveMonitor::SetExclusive16(std::size_t core_index, VAddr addr) {
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+ monitor.Mark<u16>(core_index, addr, 2, [&]() -> u16 { return memory.Read16(addr); });
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+}
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+
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+void DynarmicExclusiveMonitor::SetExclusive32(std::size_t core_index, VAddr addr) {
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+ monitor.Mark<u32>(core_index, addr, 4, [&]() -> u32 { return memory.Read32(addr); });
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+}
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+
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+void DynarmicExclusiveMonitor::SetExclusive64(std::size_t core_index, VAddr addr) {
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+ monitor.Mark<u64>(core_index, addr, 8, [&]() -> u64 { return memory.Read64(addr); });
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+}
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+
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+void DynarmicExclusiveMonitor::SetExclusive128(std::size_t core_index, VAddr addr) {
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+ monitor.Mark<u128>(core_index, addr, 16, [&]() -> u128 {
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+ u128 result;
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+ result[0] = memory.Read64(addr);
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+ result[1] = memory.Read64(addr + 8);
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+ return result;
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+ });
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}
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}
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void DynarmicExclusiveMonitor::ClearExclusive() {
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void DynarmicExclusiveMonitor::ClearExclusive() {
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@@ -294,28 +330,32 @@ void DynarmicExclusiveMonitor::ClearExclusive() {
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}
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}
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bool DynarmicExclusiveMonitor::ExclusiveWrite8(std::size_t core_index, VAddr vaddr, u8 value) {
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bool DynarmicExclusiveMonitor::ExclusiveWrite8(std::size_t core_index, VAddr vaddr, u8 value) {
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- return monitor.DoExclusiveOperation(core_index, vaddr, 1, [&] { memory.Write8(vaddr, value); });
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+ return monitor.DoExclusiveOperation<u8>(core_index, vaddr, 1, [&](u8 expected) -> bool {
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+ return memory.WriteExclusive8(vaddr, value, expected);
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+ });
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}
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}
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bool DynarmicExclusiveMonitor::ExclusiveWrite16(std::size_t core_index, VAddr vaddr, u16 value) {
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bool DynarmicExclusiveMonitor::ExclusiveWrite16(std::size_t core_index, VAddr vaddr, u16 value) {
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- return monitor.DoExclusiveOperation(core_index, vaddr, 2,
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- [&] { memory.Write16(vaddr, value); });
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+ return monitor.DoExclusiveOperation<u16>(core_index, vaddr, 2, [&](u16 expected) -> bool {
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+ return memory.WriteExclusive16(vaddr, value, expected);
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+ });
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}
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}
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bool DynarmicExclusiveMonitor::ExclusiveWrite32(std::size_t core_index, VAddr vaddr, u32 value) {
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bool DynarmicExclusiveMonitor::ExclusiveWrite32(std::size_t core_index, VAddr vaddr, u32 value) {
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- return monitor.DoExclusiveOperation(core_index, vaddr, 4,
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- [&] { memory.Write32(vaddr, value); });
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+ return monitor.DoExclusiveOperation<u32>(core_index, vaddr, 4, [&](u32 expected) -> bool {
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+ return memory.WriteExclusive32(vaddr, value, expected);
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+ });
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}
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}
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bool DynarmicExclusiveMonitor::ExclusiveWrite64(std::size_t core_index, VAddr vaddr, u64 value) {
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bool DynarmicExclusiveMonitor::ExclusiveWrite64(std::size_t core_index, VAddr vaddr, u64 value) {
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- return monitor.DoExclusiveOperation(core_index, vaddr, 8,
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- [&] { memory.Write64(vaddr, value); });
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+ return monitor.DoExclusiveOperation<u64>(core_index, vaddr, 8, [&](u64 expected) -> bool {
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+ return memory.WriteExclusive64(vaddr, value, expected);
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+ });
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}
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}
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bool DynarmicExclusiveMonitor::ExclusiveWrite128(std::size_t core_index, VAddr vaddr, u128 value) {
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bool DynarmicExclusiveMonitor::ExclusiveWrite128(std::size_t core_index, VAddr vaddr, u128 value) {
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- return monitor.DoExclusiveOperation(core_index, vaddr, 16, [&] {
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- memory.Write64(vaddr + 0, value[0]);
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- memory.Write64(vaddr + 8, value[1]);
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+ return monitor.DoExclusiveOperation<u128>(core_index, vaddr, 16, [&](u128 expected) -> bool {
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+ return memory.WriteExclusive128(vaddr, value, expected);
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});
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});
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}
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}
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