Merge pull request #559 from lioncash/clean

arm: Some cleanup. Also fixed the initial ARM mode that is emulated.

src/core/arm/dyncom/arm_dyncom.cpp

@@ -23,7 +23,7 @@ ARM_DynCom::ARM_DynCom() {
 
     ARMul_NewState((ARMul_State*)state.get());
 
-    state->abort_model = 0;
+    state->abort_model = ABORT_BASE_RESTORED;
     state->cpu = (cpu_config_t*)&s_arm11_cpu_info;
     state->bigendSig = LOW;
 
@@ -34,7 +34,7 @@ ARM_DynCom::ARM_DynCom() {
     ARMul_CoProInit(state.get());
     ARMul_Reset(state.get());
     state->NextInstr = RESUME; // NOTE: This will be overwritten by LoadContext
-    state->Emulate = 3;
+    state->Emulate = RUN;
 
     state->Reg[15] = 0x00000000;
     state->Reg[13] = 0x10000000; // Set stack pointer to the top of the stack

src/core/arm/interpreter/arminit.cpp

@@ -74,7 +74,7 @@ ARMul_State* ARMul_NewState(ARMul_State* state)
     for (unsigned int i = 0; i < 7; i++)
         state->Spsr[i] = 0;
 
-    state->Mode = 0;
+    state->Mode = USER32MODE;
 
     state->VectorCatch = 0;
     state->Aborted = false;

src/core/arm/skyeye_common/armdefs.h

@@ -35,15 +35,27 @@
 #define BITS(s, a, b) ((s << ((sizeof(s) * 8 - 1) - b)) >> (sizeof(s) * 8 - b + a - 1))
 #define BIT(s, n) ((s >> (n)) & 1)
 
-#define LOW 0
-#define HIGH 1
-#define LOWHIGH 1
-#define HIGHLOW 2
-
-//the define of cachetype
-#define NONCACHE  0
-#define DATACACHE  1
-#define INSTCACHE  2
+// Signal levels
+enum {
+    LOW     = 0,
+    HIGH    = 1,
+    LOWHIGH = 1,
+    HIGHLOW = 2
+};
+
+// Cache types
+enum {
+    NONCACHE  = 0,
+    DATACACHE = 1,
+    INSTCACHE = 2,
+};
+
+// Abort models
+enum {
+    ABORT_BASE_RESTORED = 0,
+    ABORT_EARLY         = 1,
+    ABORT_BASE_UPDATED  = 2
+};
 
 #define POS(i) ( (~(i)) >> 31 )
 #define NEG(i) ( (i) >> 31 )

src/core/arm/skyeye_common/armemu.h

@@ -76,24 +76,28 @@
 #define R15MODE (state->Reg[15] & R15MODEBITS)
 
 // Different ways to start the next instruction.
-#define SEQ           0
-#define NONSEQ        1
-#define PCINCEDSEQ    2
-#define PCINCEDNONSEQ 3
-#define PRIMEPIPE     4
-#define RESUME        8
+enum {
+    SEQ           = 0,
+    NONSEQ        = 1,
+    PCINCEDSEQ    = 2,
+    PCINCEDNONSEQ = 3,
+    PRIMEPIPE     = 4,
+    RESUME        = 8
+};
+
+// Values for Emulate.
+enum {
+    STOP       = 0, // Stop
+    CHANGEMODE = 1, // Change mode
+    ONCE       = 2, // Execute just one interation
+    RUN        = 3  // Continuous execution
+};
 
 #define FLUSHPIPE state->NextInstr |= PRIMEPIPE
 
 // Macro to rotate n right by b bits.
 #define ROTATER(n, b) (((n) >> (b)) | ((n) << (32 - (b))))
 
-// Values for Emulate.
-#define STOP            0 // stop
-#define CHANGEMODE      1 // change mode
-#define ONCE            2 // execute just one interation
-#define RUN             3 // continuous execution
-
 // Stuff that is shared across modes.
 extern unsigned ARMul_MultTable[]; // Number of I cycles for a mult.
 extern ARMword ARMul_ImmedTable[]; // Immediate DP LHS values.