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@@ -7,14 +7,17 @@
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#include <dynarmic/A32/a32.h>
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#include <dynarmic/A32/a32.h>
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#include <dynarmic/A32/config.h>
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#include <dynarmic/A32/config.h>
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#include <dynarmic/A32/context.h>
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#include <dynarmic/A32/context.h>
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+#include "common/logging/log.h"
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+#include "common/page_table.h"
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#include "core/arm/cpu_interrupt_handler.h"
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#include "core/arm/cpu_interrupt_handler.h"
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#include "core/arm/dynarmic/arm_dynarmic_32.h"
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#include "core/arm/dynarmic/arm_dynarmic_32.h"
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-#include "core/arm/dynarmic/arm_dynarmic_64.h"
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#include "core/arm/dynarmic/arm_dynarmic_cp15.h"
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#include "core/arm/dynarmic/arm_dynarmic_cp15.h"
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+#include "core/arm/dynarmic/arm_exclusive_monitor.h"
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#include "core/core.h"
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#include "core/core.h"
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#include "core/core_timing.h"
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#include "core/core_timing.h"
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#include "core/hle/kernel/svc.h"
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#include "core/hle/kernel/svc.h"
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#include "core/memory.h"
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#include "core/memory.h"
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+#include "core/settings.h"
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namespace Core {
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namespace Core {
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@@ -48,6 +51,19 @@ public:
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parent.system.Memory().Write64(vaddr, value);
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parent.system.Memory().Write64(vaddr, value);
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}
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}
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+ bool MemoryWriteExclusive8(u32 vaddr, u8 value, u8 expected) override {
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+ return parent.system.Memory().WriteExclusive8(vaddr, value, expected);
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+ }
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+ bool MemoryWriteExclusive16(u32 vaddr, u16 value, u16 expected) override {
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+ return parent.system.Memory().WriteExclusive16(vaddr, value, expected);
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+ }
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+ bool MemoryWriteExclusive32(u32 vaddr, u32 value, u32 expected) override {
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+ return parent.system.Memory().WriteExclusive32(vaddr, value, expected);
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+ }
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+ bool MemoryWriteExclusive64(u32 vaddr, u64 value, u64 expected) override {
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+ return parent.system.Memory().WriteExclusive64(vaddr, value, expected);
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+ }
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+
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void InterpreterFallback(u32 pc, std::size_t num_instructions) override {
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void InterpreterFallback(u32 pc, std::size_t num_instructions) override {
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UNIMPLEMENTED_MSG("This should never happen, pc = {:08X}, code = {:08X}", pc,
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UNIMPLEMENTED_MSG("This should never happen, pc = {:08X}, code = {:08X}", pc,
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MemoryReadCode(pc));
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MemoryReadCode(pc));
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@@ -110,6 +126,27 @@ std::shared_ptr<Dynarmic::A32::Jit> ARM_Dynarmic_32::MakeJit(Common::PageTable&
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// config.page_table = &page_table.pointers;
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// config.page_table = &page_table.pointers;
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config.coprocessors[15] = cp15;
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config.coprocessors[15] = cp15;
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config.define_unpredictable_behaviour = true;
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config.define_unpredictable_behaviour = true;
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+ static constexpr std::size_t PAGE_BITS = 12;
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+ static constexpr std::size_t NUM_PAGE_TABLE_ENTRIES = 1 << (32 - PAGE_BITS);
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+ config.page_table = reinterpret_cast<std::array<std::uint8_t*, NUM_PAGE_TABLE_ENTRIES>*>(
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+ page_table.pointers.data());
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+ config.absolute_offset_page_table = true;
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+ config.detect_misaligned_access_via_page_table = 16 | 32 | 64 | 128;
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+ config.only_detect_misalignment_via_page_table_on_page_boundary = true;
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+
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+ // Multi-process state
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+ config.processor_id = core_index;
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+ config.global_monitor = &exclusive_monitor.monitor;
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+
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+ // Timing
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+ config.wall_clock_cntpct = uses_wall_clock;
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+
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+ // Optimizations
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+ if (Settings::values.disable_cpu_opt) {
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+ config.enable_optimizations = false;
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+ config.enable_fast_dispatch = false;
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+ }
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+
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return std::make_unique<Dynarmic::A32::Jit>(config);
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return std::make_unique<Dynarmic::A32::Jit>(config);
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}
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}
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@@ -178,7 +215,7 @@ void ARM_Dynarmic_32::SetTPIDR_EL0(u64 value) {
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}
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}
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void ARM_Dynarmic_32::ChangeProcessorId(std::size_t new_core_id) {
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void ARM_Dynarmic_32::ChangeProcessorId(std::size_t new_core_id) {
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- // jit->ChangeProcessorId(new_core_id);
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+ jit->ChangeProcessorID(new_core_id);
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}
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}
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void ARM_Dynarmic_32::SaveContext(ThreadContext32& ctx) {
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void ARM_Dynarmic_32::SaveContext(ThreadContext32& ctx) {
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