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+// Copyright 2021 yuzu Emulator Project
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+// Licensed under GPLv2 or any later version
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+// Refer to the license.txt file included.
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+
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+#include "shader_recompiler/frontend/maxwell/translate/impl/half_floating_point_helper.h"
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+
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+namespace Shader::Maxwell {
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+namespace {
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+void HSET2(TranslatorVisitor& v, u64 insn, const IR::U32& src_b, bool bf, bool ftz, bool neg_b,
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+ bool abs_b, FPCompareOp compare_op, Swizzle swizzle_b) {
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+ union {
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+ u64 insn;
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+ BitField<0, 8, IR::Reg> dest_reg;
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+ BitField<8, 8, IR::Reg> src_a_reg;
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+ BitField<39, 3, IR::Pred> pred;
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+ BitField<42, 1, u64> neg_pred;
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+ BitField<43, 1, u64> neg_a;
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+ BitField<45, 2, BooleanOp> bop;
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+ BitField<44, 1, u64> abs_a;
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+ BitField<47, 2, Swizzle> swizzle_a;
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+ } const hset2{insn};
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+
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+ auto [lhs_a, rhs_a]{Extract(v.ir, v.X(hset2.src_a_reg), hset2.swizzle_a)};
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+ auto [lhs_b, rhs_b]{Extract(v.ir, src_b, swizzle_b)};
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+ // TODO: Implement FP16 FloatingPointCompare
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+ //if (lhs_a.Type() != lhs_b.Type()) {
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+ if (lhs_a.Type() == IR::Type::F16) {
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+ lhs_a = v.ir.FPConvert(32, lhs_a);
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+ rhs_a = v.ir.FPConvert(32, rhs_a);
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+ }
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+ if (lhs_b.Type() == IR::Type::F16) {
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+ lhs_b = v.ir.FPConvert(32, lhs_b);
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+ rhs_b = v.ir.FPConvert(32, rhs_b);
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+ }
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+ //}
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+
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+ lhs_a = v.ir.FPAbsNeg(lhs_a, hset2.abs_a != 0, hset2.neg_a != 0);
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+ rhs_a = v.ir.FPAbsNeg(rhs_a, hset2.abs_a != 0, hset2.neg_a != 0);
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+
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+ lhs_b = v.ir.FPAbsNeg(lhs_b, abs_b, neg_b);
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+ rhs_b = v.ir.FPAbsNeg(rhs_b, abs_b, neg_b);
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+
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+ const IR::FpControl control{
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+ .no_contraction{false},
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+ .rounding{IR::FpRounding::DontCare},
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+ .fmz_mode{ftz ? IR::FmzMode::FTZ : IR::FmzMode::None},
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+ };
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+
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+ IR::U1 pred{v.ir.GetPred(hset2.pred)};
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+ if (hset2.neg_pred != 0) {
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+ pred = v.ir.LogicalNot(pred);
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+ }
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+ const IR::U1 cmp_result_lhs{FloatingPointCompare(v.ir, lhs_a, lhs_b, compare_op, control)};
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+ const IR::U1 cmp_result_rhs{FloatingPointCompare(v.ir, rhs_a, rhs_b, compare_op, control)};
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+ const IR::U1 bop_result_lhs{PredicateCombine(v.ir, cmp_result_lhs, pred, hset2.bop)};
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+ const IR::U1 bop_result_rhs{PredicateCombine(v.ir, cmp_result_rhs, pred, hset2.bop)};
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+
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+ const u32 true_value = bf ? 0x3c00 : 0xffff;
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+ const IR::U32 true_val_lhs{v.ir.Imm32(true_value)};
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+ const IR::U32 true_val_rhs{v.ir.Imm32(true_value << 16)};
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+ const IR::U32 fail_result{v.ir.Imm32(0)};
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+ const IR::U32 result_lhs{v.ir.Select(bop_result_lhs, true_val_lhs, fail_result)};
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+ const IR::U32 result_rhs{v.ir.Select(bop_result_rhs, true_val_rhs, fail_result)};
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+
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+ v.X(hset2.dest_reg, IR::U32{v.ir.BitwiseOr(result_lhs, result_rhs)});
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+}
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+} // Anonymous namespace
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+
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+void TranslatorVisitor::HSET2_reg(u64 insn) {
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+ union {
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+ u64 insn;
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+ BitField<30, 1, u64> abs_b;
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+ BitField<49, 1, u64> bf;
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+ BitField<31, 1, u64> neg_b;
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+ BitField<50, 1, u64> ftz;
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+ BitField<35, 4, FPCompareOp> compare_op;
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+ BitField<28, 2, Swizzle> swizzle_b;
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+ } const hset2{insn};
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+ HSET2(*this, insn, GetReg20(insn), hset2.bf != 0, hset2.ftz != 0, hset2.neg_b != 0,
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+ hset2.abs_b != 0, hset2.compare_op, hset2.swizzle_b);
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+}
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+
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+void TranslatorVisitor::HSET2_cbuf(u64 insn) {
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+ union {
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+ u64 insn;
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+ BitField<53, 1, u64> bf;
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+ BitField<56, 1, u64> neg_b;
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+ BitField<54, 1, u64> ftz;
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+ BitField<49, 4, FPCompareOp> compare_op;
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+ } const hset2{insn};
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+
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+ HSET2(*this, insn, GetCbuf(insn), hset2.bf != 0, hset2.ftz != 0, hset2.neg_b != 0, false,
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+ hset2.compare_op, Swizzle::F32);
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+}
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+
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+void TranslatorVisitor::HSET2_imm(u64 insn) {
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+ union {
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+ u64 insn;
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+ BitField<53, 1, u64> bf;
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+ BitField<54, 1, u64> ftz;
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+ BitField<49, 4, FPCompareOp> compare_op;
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+ BitField<56, 1, u64> neg_high;
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+ BitField<30, 9, u64> high;
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+ BitField<29, 1, u64> neg_low;
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+ BitField<20, 9, u64> low;
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+ } const hset2{insn};
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+
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+ const u32 imm{static_cast<u32>(hset2.low << 6) | ((hset2.neg_low != 0 ? 1 : 0) << 15) |
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+ static_cast<u32>(hset2.high << 22) | ((hset2.neg_high != 0 ? 1 : 0) << 31)};
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+
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+ HSET2(*this, insn, ir.Imm32(imm), hset2.bf != 0, hset2.ftz != 0, false, false,
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+ hset2.compare_op, Swizzle::H1_H0);
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+}
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+
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+} // namespace Shader::Maxwell
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FernandoS27