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@@ -221,7 +221,18 @@ struct Regs {
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u32 trigger_draw;
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u32 trigger_draw;
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u32 trigger_draw_indexed;
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u32 trigger_draw_indexed;
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- INSERT_PADDING_WORDS(0x8a);
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+ INSERT_PADDING_WORDS(0x2e);
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+
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+ enum class TriangleTopology : u32 {
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+ List = 0,
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+ Strip = 1,
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+ Fan = 2,
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+ ListIndexed = 3, // TODO: No idea if this is correct
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+ };
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+
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+ BitField<8, 2, TriangleTopology> triangle_topology;
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+
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+ INSERT_PADDING_WORDS(0x5b);
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// Offset to shader program entry point (in words)
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// Offset to shader program entry point (in words)
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BitField<0, 16, u32> vs_main_offset;
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BitField<0, 16, u32> vs_main_offset;
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@@ -334,6 +345,7 @@ struct Regs {
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ADD_FIELD(num_vertices);
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ADD_FIELD(num_vertices);
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ADD_FIELD(trigger_draw);
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ADD_FIELD(trigger_draw);
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ADD_FIELD(trigger_draw_indexed);
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ADD_FIELD(trigger_draw_indexed);
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+ ADD_FIELD(triangle_topology);
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ADD_FIELD(vs_main_offset);
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ADD_FIELD(vs_main_offset);
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ADD_FIELD(vs_input_register_map);
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ADD_FIELD(vs_input_register_map);
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ADD_FIELD(vs_uniform_setup);
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ADD_FIELD(vs_uniform_setup);
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@@ -386,6 +398,7 @@ ASSERT_REG_POSITION(index_array, 0x227);
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ASSERT_REG_POSITION(num_vertices, 0x228);
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ASSERT_REG_POSITION(num_vertices, 0x228);
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ASSERT_REG_POSITION(trigger_draw, 0x22e);
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ASSERT_REG_POSITION(trigger_draw, 0x22e);
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ASSERT_REG_POSITION(trigger_draw_indexed, 0x22f);
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ASSERT_REG_POSITION(trigger_draw_indexed, 0x22f);
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+ASSERT_REG_POSITION(triangle_topology, 0x25e);
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ASSERT_REG_POSITION(vs_main_offset, 0x2ba);
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ASSERT_REG_POSITION(vs_main_offset, 0x2ba);
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ASSERT_REG_POSITION(vs_input_register_map, 0x2bb);
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ASSERT_REG_POSITION(vs_input_register_map, 0x2bb);
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ASSERT_REG_POSITION(vs_uniform_setup, 0x2c0);
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ASSERT_REG_POSITION(vs_uniform_setup, 0x2c0);
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