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@@ -36,6 +36,48 @@ u32 ShaderIR::DecodeArithmetic(BasicBlock& bb, u32 pc) {
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SetRegister(bb, instr.gpr0, op_b);
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break;
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}
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+ case OpCode::Id::FMUL_C:
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+ case OpCode::Id::FMUL_R:
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+ case OpCode::Id::FMUL_IMM: {
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+ // FMUL does not have 'abs' bits and only the second operand has a 'neg' bit.
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+ UNIMPLEMENTED_IF_MSG(instr.fmul.tab5cb8_2 != 0, "FMUL tab5cb8_2({}) is not implemented",
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+ instr.fmul.tab5cb8_2.Value());
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+ UNIMPLEMENTED_IF_MSG(
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+ instr.fmul.tab5c68_0 != 1, "FMUL tab5cb8_0({}) is not implemented",
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+ instr.fmul.tab5c68_0.Value()); // SMO typical sends 1 here which seems to be the default
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+ UNIMPLEMENTED_IF_MSG(instr.generates_cc,
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+ "Condition codes generation in FMUL is not implemented");
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+
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+ op_b = GetOperandAbsNegFloat(op_b, false, instr.fmul.negate_b);
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+
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+ // TODO(Rodrigo): Should precise be used when there's a postfactor?
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+ Node value = Operation(OperationCode::FMul, PRECISE, op_a, op_b);
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+
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+ if (instr.fmul.postfactor != 0) {
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+ auto postfactor = static_cast<s32>(instr.fmul.postfactor);
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+
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+ // Postfactor encoded as 3-bit 1's complement in instruction, interpreted with below
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+ // logic.
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+ if (postfactor >= 4) {
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+ postfactor = 7 - postfactor;
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+ } else {
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+ postfactor = 0 - postfactor;
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+ }
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+
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+ if (postfactor > 0) {
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+ value = Operation(OperationCode::FMul, NO_PRECISE, value,
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+ Immediate(static_cast<f32>(1 << postfactor)));
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+ } else {
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+ value = Operation(OperationCode::FDiv, NO_PRECISE, value,
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+ Immediate(static_cast<f32>(1 << -postfactor)));
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+ }
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+ }
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+
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+ value = GetSaturatedFloat(value, instr.alu.saturate_d);
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+
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+ SetRegister(bb, instr.gpr0, value);
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+ break;
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+ }
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default:
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UNIMPLEMENTED_MSG("Unhandled arithmetic instruction: {}", opcode->get().GetName());
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}
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