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@@ -0,0 +1,953 @@
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+/* armsupp.c -- ARMulator support code: ARM6 Instruction Emulator.
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+ Copyright (C) 1994 Advanced RISC Machines Ltd.
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+
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+ This program is free software; you can redistribute it and/or modify
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+ it under the terms of the GNU General Public License as published by
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+ the Free Software Foundation; either version 2 of the License, or
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+ (at your option) any later version.
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+
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+ This program is distributed in the hope that it will be useful,
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+ but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ GNU General Public License for more details.
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+
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+ You should have received a copy of the GNU General Public License
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+ along with this program; if not, write to the Free Software
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+ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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+
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+#include "armdefs.h"
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+#include "armemu.h"
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+//#include "ansidecl.h"
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+#include "skyeye_defs.h"
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+unsigned xscale_cp15_cp_access_allowed (ARMul_State * state, unsigned reg,
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+ unsigned cpnum);
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+//extern int skyeye_instr_debug;
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+/* Definitions for the support routines. */
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+
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+static ARMword ModeToBank (ARMword);
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+static void EnvokeList (ARMul_State *, unsigned int, unsigned int);
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+
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+struct EventNode
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+{ /* An event list node. */
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+ unsigned (*func) (ARMul_State *); /* The function to call. */
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+ struct EventNode *next;
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+};
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+
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+/* This routine returns the value of a register from a mode. */
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+
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+ARMword
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+ARMul_GetReg (ARMul_State * state, unsigned mode, unsigned reg)
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+{
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+ mode &= MODEBITS;
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+ if (mode != state->Mode)
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+ return (state->RegBank[ModeToBank ((ARMword) mode)][reg]);
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+ else
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+ return (state->Reg[reg]);
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+}
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+
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+/* This routine sets the value of a register for a mode. */
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+
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+void
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+ARMul_SetReg (ARMul_State * state, unsigned mode, unsigned reg, ARMword value)
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+{
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+ mode &= MODEBITS;
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+ if (mode != state->Mode)
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+ state->RegBank[ModeToBank ((ARMword) mode)][reg] = value;
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+ else
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+ state->Reg[reg] = value;
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+}
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+
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+/* This routine returns the value of the PC, mode independently. */
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+
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+ARMword
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+ARMul_GetPC (ARMul_State * state)
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+{
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+ if (state->Mode > SVC26MODE)
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+ return state->Reg[15];
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+ else
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+ return R15PC;
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+}
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+
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+/* This routine returns the value of the PC, mode independently. */
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+
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+ARMword
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+ARMul_GetNextPC (ARMul_State * state)
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+{
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+ if (state->Mode > SVC26MODE)
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+ return state->Reg[15] + isize;
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+ else
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+ return (state->Reg[15] + isize) & R15PCBITS;
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+}
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+
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+/* This routine sets the value of the PC. */
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+
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+void
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+ARMul_SetPC (ARMul_State * state, ARMword value)
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+{
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+ if (ARMul_MODE32BIT)
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+ state->Reg[15] = value & PCBITS;
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+ else
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+ state->Reg[15] = R15CCINTMODE | (value & R15PCBITS);
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+ FLUSHPIPE;
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+}
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+
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+/* This routine returns the value of register 15, mode independently. */
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+
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+ARMword
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+ARMul_GetR15 (ARMul_State * state)
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+{
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+ if (state->Mode > SVC26MODE)
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+ return (state->Reg[15]);
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+ else
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+ return (R15PC | ECC | ER15INT | EMODE);
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+}
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+
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+/* This routine sets the value of Register 15. */
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+
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+void
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+ARMul_SetR15 (ARMul_State * state, ARMword value)
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+{
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+ if (ARMul_MODE32BIT)
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+ state->Reg[15] = value & PCBITS;
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+ else {
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+ state->Reg[15] = value;
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+ ARMul_R15Altered (state);
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+ }
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+ FLUSHPIPE;
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+}
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+
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+/* This routine returns the value of the CPSR. */
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+
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+ARMword
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+ARMul_GetCPSR (ARMul_State * state)
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+{
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+ //chy 2003-08-20: below is from gdb20030716, maybe isn't suitable for system simulator
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+ //return (CPSR | state->Cpsr); for gdb20030716
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+ return (CPSR); //had be tested in old skyeye with gdb5.0-5.3
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+}
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+
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+/* This routine sets the value of the CPSR. */
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+
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+void
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+ARMul_SetCPSR (ARMul_State * state, ARMword value)
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+{
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+ state->Cpsr = value;
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+ ARMul_CPSRAltered (state);
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+}
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+
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+/* This routine does all the nasty bits involved in a write to the CPSR,
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+ including updating the register bank, given a MSR instruction. */
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+
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+void
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+ARMul_FixCPSR (ARMul_State * state, ARMword instr, ARMword rhs)
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+{
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+ state->Cpsr = ARMul_GetCPSR (state);
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+ //chy 2006-02-16 , should not consider system mode, don't conside 26bit mode
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+ if (state->Mode != USER26MODE && state->Mode != USER32MODE ) {
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+ /* In user mode, only write flags. */
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+ if (BIT (16))
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+ SETPSR_C (state->Cpsr, rhs);
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+ if (BIT (17))
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+ SETPSR_X (state->Cpsr, rhs);
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+ if (BIT (18))
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+ SETPSR_S (state->Cpsr, rhs);
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+ }
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+ if (BIT (19))
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+ SETPSR_F (state->Cpsr, rhs);
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+ ARMul_CPSRAltered (state);
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+}
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+
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+/* Get an SPSR from the specified mode. */
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+
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+ARMword
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+ARMul_GetSPSR (ARMul_State * state, ARMword mode)
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+{
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+ ARMword bank = ModeToBank (mode & MODEBITS);
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+
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+ if (!BANK_CAN_ACCESS_SPSR (bank))
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+ return ARMul_GetCPSR (state);
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+
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+ return state->Spsr[bank];
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+}
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+
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+/* This routine does a write to an SPSR. */
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+
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+void
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+ARMul_SetSPSR (ARMul_State * state, ARMword mode, ARMword value)
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+{
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+ ARMword bank = ModeToBank (mode & MODEBITS);
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+
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+ if (BANK_CAN_ACCESS_SPSR (bank))
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+ state->Spsr[bank] = value;
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+}
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+
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+/* This routine does a write to the current SPSR, given an MSR instruction. */
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+
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+void
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+ARMul_FixSPSR (ARMul_State * state, ARMword instr, ARMword rhs)
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+{
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+ if (BANK_CAN_ACCESS_SPSR (state->Bank)) {
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+ if (BIT (16))
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+ SETPSR_C (state->Spsr[state->Bank], rhs);
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+ if (BIT (17))
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+ SETPSR_X (state->Spsr[state->Bank], rhs);
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+ if (BIT (18))
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+ SETPSR_S (state->Spsr[state->Bank], rhs);
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+ if (BIT (19))
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+ SETPSR_F (state->Spsr[state->Bank], rhs);
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+ }
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+}
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+
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+/* This routine updates the state of the emulator after the Cpsr has been
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+ changed. Both the processor flags and register bank are updated. */
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+
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+void
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+ARMul_CPSRAltered (ARMul_State * state)
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+{
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+ ARMword oldmode;
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+
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+ if (state->prog32Sig == LOW)
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+ state->Cpsr &= (CCBITS | INTBITS | R15MODEBITS);
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+
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+ oldmode = state->Mode;
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+
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+ if (state->Mode != (state->Cpsr & MODEBITS)) {
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+ state->Mode =
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+ ARMul_SwitchMode (state, state->Mode,
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+ state->Cpsr & MODEBITS);
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+
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+ state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
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+ }
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+ //state->Cpsr &= ~MODEBITS;
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+
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+ ASSIGNINT (state->Cpsr & INTBITS);
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+ //state->Cpsr &= ~INTBITS;
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+ ASSIGNN ((state->Cpsr & NBIT) != 0);
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+ //state->Cpsr &= ~NBIT;
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+ ASSIGNZ ((state->Cpsr & ZBIT) != 0);
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+ //state->Cpsr &= ~ZBIT;
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+ ASSIGNC ((state->Cpsr & CBIT) != 0);
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+ //state->Cpsr &= ~CBIT;
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+ ASSIGNV ((state->Cpsr & VBIT) != 0);
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+ //state->Cpsr &= ~VBIT;
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+ ASSIGNS ((state->Cpsr & SBIT) != 0);
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+ //state->Cpsr &= ~SBIT;
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+#ifdef MODET
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+ ASSIGNT ((state->Cpsr & TBIT) != 0);
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+ //state->Cpsr &= ~TBIT;
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+#endif
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+
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+ if (oldmode > SVC26MODE) {
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+ if (state->Mode <= SVC26MODE) {
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+ state->Emulate = CHANGEMODE;
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+ state->Reg[15] = ECC | ER15INT | EMODE | R15PC;
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+ }
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+ }
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+ else {
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+ if (state->Mode > SVC26MODE) {
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+ state->Emulate = CHANGEMODE;
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+ state->Reg[15] = R15PC;
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+ }
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+ else
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+ state->Reg[15] = ECC | ER15INT | EMODE | R15PC;
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+ }
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+}
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+
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+/* This routine updates the state of the emulator after register 15 has
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+ been changed. Both the processor flags and register bank are updated.
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+ This routine should only be called from a 26 bit mode. */
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+
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+void
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+ARMul_R15Altered (ARMul_State * state)
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+{
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+ if (state->Mode != R15MODE) {
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+ state->Mode = ARMul_SwitchMode (state, state->Mode, R15MODE);
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+ state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
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+ }
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+
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+ if (state->Mode > SVC26MODE)
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+ state->Emulate = CHANGEMODE;
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+
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+ ASSIGNR15INT (R15INT);
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+
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+ ASSIGNN ((state->Reg[15] & NBIT) != 0);
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+ ASSIGNZ ((state->Reg[15] & ZBIT) != 0);
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+ ASSIGNC ((state->Reg[15] & CBIT) != 0);
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+ ASSIGNV ((state->Reg[15] & VBIT) != 0);
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+}
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+
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+/* This routine controls the saving and restoring of registers across mode
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+ changes. The regbank matrix is largely unused, only rows 13 and 14 are
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+ used across all modes, 8 to 14 are used for FIQ, all others use the USER
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+ column. It's easier this way. old and new parameter are modes numbers.
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+ Notice the side effect of changing the Bank variable. */
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+
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+ARMword
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+ARMul_SwitchMode (ARMul_State * state, ARMword oldmode, ARMword newmode)
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+{
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+ unsigned i;
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+ ARMword oldbank;
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+ ARMword newbank;
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+ static int revision_value = 53;
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+
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+ oldbank = ModeToBank (oldmode);
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+ newbank = state->Bank = ModeToBank (newmode);
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+
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+ /* Do we really need to do it? */
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+ if (oldbank != newbank) {
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+ if (oldbank == 3 && newbank == 2) {
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+ //printf("icounter is %d PC is %x MODE CHANGED : %d --> %d\n", state->NumInstrs, state->pc, oldbank, newbank);
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+ if (state->NumInstrs >= 5832487) {
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+// printf("%d, ", state->NumInstrs + revision_value);
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+// printf("revision_value : %d\n", revision_value);
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+ revision_value ++;
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+ }
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+ }
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+ /* Save away the old registers. */
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+ switch (oldbank) {
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+ case USERBANK:
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+ case IRQBANK:
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+ case SVCBANK:
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+ case ABORTBANK:
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+ case UNDEFBANK:
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+ if (newbank == FIQBANK)
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+ for (i = 8; i < 13; i++)
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+ state->RegBank[USERBANK][i] =
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+ state->Reg[i];
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+ state->RegBank[oldbank][13] = state->Reg[13];
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+ state->RegBank[oldbank][14] = state->Reg[14];
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+ break;
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+ case FIQBANK:
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+ for (i = 8; i < 15; i++)
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+ state->RegBank[FIQBANK][i] = state->Reg[i];
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+ break;
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+ case DUMMYBANK:
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+ for (i = 8; i < 15; i++)
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+ state->RegBank[DUMMYBANK][i] = 0;
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+ break;
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+ default:
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+ abort ();
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+ }
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+
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+ /* Restore the new registers. */
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+ switch (newbank) {
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+ case USERBANK:
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+ case IRQBANK:
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+ case SVCBANK:
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+ case ABORTBANK:
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+ case UNDEFBANK:
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+ if (oldbank == FIQBANK)
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+ for (i = 8; i < 13; i++)
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+ state->Reg[i] =
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+ state->RegBank[USERBANK][i];
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+ state->Reg[13] = state->RegBank[newbank][13];
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+ state->Reg[14] = state->RegBank[newbank][14];
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+ break;
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+ case FIQBANK:
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+ for (i = 8; i < 15; i++)
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+ state->Reg[i] = state->RegBank[FIQBANK][i];
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+ break;
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+ case DUMMYBANK:
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+ for (i = 8; i < 15; i++)
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+ state->Reg[i] = 0;
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+ break;
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+ default:
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+ abort ();
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+ }
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+ }
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+
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+ return newmode;
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+}
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+
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+/* Given a processor mode, this routine returns the
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+ register bank that will be accessed in that mode. */
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+
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+static ARMword
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+ModeToBank (ARMword mode)
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+{
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+ static ARMword bankofmode[] = {
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+ USERBANK, FIQBANK, IRQBANK, SVCBANK,
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+ DUMMYBANK, DUMMYBANK, DUMMYBANK, DUMMYBANK,
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+ DUMMYBANK, DUMMYBANK, DUMMYBANK, DUMMYBANK,
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+ DUMMYBANK, DUMMYBANK, DUMMYBANK, DUMMYBANK,
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+ USERBANK, FIQBANK, IRQBANK, SVCBANK,
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+ DUMMYBANK, DUMMYBANK, DUMMYBANK, ABORTBANK,
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+ DUMMYBANK, DUMMYBANK, DUMMYBANK, UNDEFBANK,
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+ DUMMYBANK, DUMMYBANK, DUMMYBANK, SYSTEMBANK
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+ };
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+
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+ if (mode >= (sizeof (bankofmode) / sizeof (bankofmode[0])))
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+ return DUMMYBANK;
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+
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+ return bankofmode[mode];
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+}
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+
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+/* Returns the register number of the nth register in a reg list. */
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+
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+unsigned
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+ARMul_NthReg (ARMword instr, unsigned number)
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+{
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+ unsigned bit, upto;
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+
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+ for (bit = 0, upto = 0; upto <= number; bit++)
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+ if (BIT (bit))
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+ upto++;
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+
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+ return (bit - 1);
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+}
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+
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+/* Assigns the N and Z flags depending on the value of result. */
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+
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+void
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+ARMul_NegZero (ARMul_State * state, ARMword result)
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+{
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+ if (NEG (result)) {
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+ SETN;
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+ CLEARZ;
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+ }
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+ else if (result == 0) {
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+ CLEARN;
|
|
|
+ SETZ;
|
|
|
+ }
|
|
|
+ else {
|
|
|
+ CLEARN;
|
|
|
+ CLEARZ;
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+/* Compute whether an addition of A and B, giving RESULT, overflowed. */
|
|
|
+
|
|
|
+int
|
|
|
+AddOverflow (ARMword a, ARMword b, ARMword result)
|
|
|
+{
|
|
|
+ return ((NEG (a) && NEG (b) && POS (result))
|
|
|
+ || (POS (a) && POS (b) && NEG (result)));
|
|
|
+}
|
|
|
+
|
|
|
+/* Compute whether a subtraction of A and B, giving RESULT, overflowed. */
|
|
|
+
|
|
|
+int
|
|
|
+SubOverflow (ARMword a, ARMword b, ARMword result)
|
|
|
+{
|
|
|
+ return ((NEG (a) && POS (b) && POS (result))
|
|
|
+ || (POS (a) && NEG (b) && NEG (result)));
|
|
|
+}
|
|
|
+
|
|
|
+/* Assigns the C flag after an addition of a and b to give result. */
|
|
|
+
|
|
|
+void
|
|
|
+ARMul_AddCarry (ARMul_State * state, ARMword a, ARMword b, ARMword result)
|
|
|
+{
|
|
|
+ ASSIGNC ((NEG (a) && NEG (b)) ||
|
|
|
+ (NEG (a) && POS (result)) || (NEG (b) && POS (result)));
|
|
|
+}
|
|
|
+
|
|
|
+/* Assigns the V flag after an addition of a and b to give result. */
|
|
|
+
|
|
|
+void
|
|
|
+ARMul_AddOverflow (ARMul_State * state, ARMword a, ARMword b, ARMword result)
|
|
|
+{
|
|
|
+ ASSIGNV (AddOverflow (a, b, result));
|
|
|
+}
|
|
|
+
|
|
|
+/* Assigns the C flag after an subtraction of a and b to give result. */
|
|
|
+
|
|
|
+void
|
|
|
+ARMul_SubCarry (ARMul_State * state, ARMword a, ARMword b, ARMword result)
|
|
|
+{
|
|
|
+ ASSIGNC ((NEG (a) && POS (b)) ||
|
|
|
+ (NEG (a) && POS (result)) || (POS (b) && POS (result)));
|
|
|
+}
|
|
|
+
|
|
|
+/* Assigns the V flag after an subtraction of a and b to give result. */
|
|
|
+
|
|
|
+void
|
|
|
+ARMul_SubOverflow (ARMul_State * state, ARMword a, ARMword b, ARMword result)
|
|
|
+{
|
|
|
+ ASSIGNV (SubOverflow (a, b, result));
|
|
|
+}
|
|
|
+
|
|
|
+/* This function does the work of generating the addresses used in an
|
|
|
+ LDC instruction. The code here is always post-indexed, it's up to the
|
|
|
+ caller to get the input address correct and to handle base register
|
|
|
+ modification. It also handles the Busy-Waiting. */
|
|
|
+
|
|
|
+void
|
|
|
+ARMul_LDC (ARMul_State * state, ARMword instr, ARMword address)
|
|
|
+{
|
|
|
+ unsigned cpab;
|
|
|
+ ARMword data;
|
|
|
+
|
|
|
+ UNDEF_LSCPCBaseWb;
|
|
|
+ //printf("SKYEYE ARMul_LDC, CPnum is %x, instr %x, addr %x\n",CPNum, instr, address);
|
|
|
+/*chy 2004-05-23 should update this function in the future,should concern dataabort*/
|
|
|
+// chy 2004-05-25 , fix it now,so needn't printf
|
|
|
+// printf("SKYEYE ARMul_LDC, should update this function!!!!!\n");
|
|
|
+ //exit(-1);
|
|
|
+
|
|
|
+ if (!CP_ACCESS_ALLOWED (state, CPNum)) {
|
|
|
+ /*
|
|
|
+ printf
|
|
|
+ ("SKYEYE ARMul_LDC,NOT ALLOW, underinstr, CPnum is %x, instr %x, addr %x\n",
|
|
|
+ CPNum, instr, address);
|
|
|
+ */
|
|
|
+ ARMul_UndefInstr (state, instr);
|
|
|
+ return;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (ADDREXCEPT (address))
|
|
|
+ INTERNALABORT (address);
|
|
|
+
|
|
|
+ cpab = (state->LDC[CPNum]) (state, ARMul_FIRST, instr, 0);
|
|
|
+ while (cpab == ARMul_BUSY) {
|
|
|
+ ARMul_Icycles (state, 1, 0);
|
|
|
+
|
|
|
+ if (IntPending (state)) {
|
|
|
+ cpab = (state->LDC[CPNum]) (state, ARMul_INTERRUPT,
|
|
|
+ instr, 0);
|
|
|
+ return;
|
|
|
+ }
|
|
|
+ else
|
|
|
+ cpab = (state->LDC[CPNum]) (state, ARMul_BUSY, instr,
|
|
|
+ 0);
|
|
|
+ }
|
|
|
+ if (cpab == ARMul_CANT) {
|
|
|
+ /*
|
|
|
+ printf
|
|
|
+ ("SKYEYE ARMul_LDC,NOT CAN, underinstr, CPnum is %x, instr %x, addr %x\n",
|
|
|
+ CPNum, instr, address);
|
|
|
+ */
|
|
|
+ CPTAKEABORT;
|
|
|
+ return;
|
|
|
+ }
|
|
|
+
|
|
|
+ cpab = (state->LDC[CPNum]) (state, ARMul_TRANSFER, instr, 0);
|
|
|
+ data = ARMul_LoadWordN (state, address);
|
|
|
+ //chy 2004-05-25
|
|
|
+ if (state->abortSig || state->Aborted)
|
|
|
+ goto L_ldc_takeabort;
|
|
|
+
|
|
|
+ BUSUSEDINCPCN;
|
|
|
+//chy 2004-05-25
|
|
|
+/*
|
|
|
+ if (BIT (21))
|
|
|
+ LSBase = state->Base;
|
|
|
+*/
|
|
|
+
|
|
|
+ cpab = (state->LDC[CPNum]) (state, ARMul_DATA, instr, data);
|
|
|
+
|
|
|
+ while (cpab == ARMul_INC) {
|
|
|
+ address += 4;
|
|
|
+ data = ARMul_LoadWordN (state, address);
|
|
|
+ //chy 2004-05-25
|
|
|
+ if (state->abortSig || state->Aborted)
|
|
|
+ goto L_ldc_takeabort;
|
|
|
+
|
|
|
+ cpab = (state->LDC[CPNum]) (state, ARMul_DATA, instr, data);
|
|
|
+ }
|
|
|
+
|
|
|
+//chy 2004-05-25
|
|
|
+ L_ldc_takeabort:
|
|
|
+ if (BIT (21)) {
|
|
|
+ if (!
|
|
|
+ ((state->abortSig || state->Aborted)
|
|
|
+ && state->lateabtSig == LOW))
|
|
|
+ LSBase = state->Base;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (state->abortSig || state->Aborted)
|
|
|
+ TAKEABORT;
|
|
|
+}
|
|
|
+
|
|
|
+/* This function does the work of generating the addresses used in an
|
|
|
+ STC instruction. The code here is always post-indexed, it's up to the
|
|
|
+ caller to get the input address correct and to handle base register
|
|
|
+ modification. It also handles the Busy-Waiting. */
|
|
|
+
|
|
|
+void
|
|
|
+ARMul_STC (ARMul_State * state, ARMword instr, ARMword address)
|
|
|
+{
|
|
|
+ unsigned cpab;
|
|
|
+ ARMword data;
|
|
|
+
|
|
|
+ UNDEF_LSCPCBaseWb;
|
|
|
+
|
|
|
+ //printf("SKYEYE ARMul_STC, CPnum is %x, instr %x, addr %x\n",CPNum, instr, address);
|
|
|
+ /*chy 2004-05-23 should update this function in the future,should concern dataabort */
|
|
|
+// skyeye_instr_debug=0;printf("SKYEYE debug end!!!!\n");
|
|
|
+// chy 2004-05-25 , fix it now,so needn't printf
|
|
|
+// printf("SKYEYE ARMul_STC, should update this function!!!!!\n");
|
|
|
+
|
|
|
+ //exit(-1);
|
|
|
+ if (!CP_ACCESS_ALLOWED (state, CPNum)) {
|
|
|
+ /*
|
|
|
+ printf
|
|
|
+ ("SKYEYE ARMul_STC,NOT ALLOW, undefinstr, CPnum is %x, instr %x, addr %x\n",
|
|
|
+ CPNum, instr, address);
|
|
|
+ */
|
|
|
+ ARMul_UndefInstr (state, instr);
|
|
|
+ return;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (ADDREXCEPT (address) || VECTORACCESS (address))
|
|
|
+ INTERNALABORT (address);
|
|
|
+
|
|
|
+ cpab = (state->STC[CPNum]) (state, ARMul_FIRST, instr, &data);
|
|
|
+ while (cpab == ARMul_BUSY) {
|
|
|
+ ARMul_Icycles (state, 1, 0);
|
|
|
+ if (IntPending (state)) {
|
|
|
+ cpab = (state->STC[CPNum]) (state, ARMul_INTERRUPT,
|
|
|
+ instr, 0);
|
|
|
+ return;
|
|
|
+ }
|
|
|
+ else
|
|
|
+ cpab = (state->STC[CPNum]) (state, ARMul_BUSY, instr,
|
|
|
+ &data);
|
|
|
+ }
|
|
|
+
|
|
|
+ if (cpab == ARMul_CANT) {
|
|
|
+ /*
|
|
|
+ printf
|
|
|
+ ("SKYEYE ARMul_STC,CANT, undefinstr, CPnum is %x, instr %x, addr %x\n",
|
|
|
+ CPNum, instr, address);
|
|
|
+ */
|
|
|
+ CPTAKEABORT;
|
|
|
+ return;
|
|
|
+ }
|
|
|
+#ifndef MODE32
|
|
|
+ if (ADDREXCEPT (address) || VECTORACCESS (address))
|
|
|
+ INTERNALABORT (address);
|
|
|
+#endif
|
|
|
+ BUSUSEDINCPCN;
|
|
|
+//chy 2004-05-25
|
|
|
+/*
|
|
|
+ if (BIT (21))
|
|
|
+ LSBase = state->Base;
|
|
|
+*/
|
|
|
+ cpab = (state->STC[CPNum]) (state, ARMul_DATA, instr, &data);
|
|
|
+ ARMul_StoreWordN (state, address, data);
|
|
|
+ //chy 2004-05-25
|
|
|
+ if (state->abortSig || state->Aborted)
|
|
|
+ goto L_stc_takeabort;
|
|
|
+
|
|
|
+ while (cpab == ARMul_INC) {
|
|
|
+ address += 4;
|
|
|
+ cpab = (state->STC[CPNum]) (state, ARMul_DATA, instr, &data);
|
|
|
+ ARMul_StoreWordN (state, address, data);
|
|
|
+ //chy 2004-05-25
|
|
|
+ if (state->abortSig || state->Aborted)
|
|
|
+ goto L_stc_takeabort;
|
|
|
+ }
|
|
|
+//chy 2004-05-25
|
|
|
+ L_stc_takeabort:
|
|
|
+ if (BIT (21)) {
|
|
|
+ if (!
|
|
|
+ ((state->abortSig || state->Aborted)
|
|
|
+ && state->lateabtSig == LOW))
|
|
|
+ LSBase = state->Base;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (state->abortSig || state->Aborted)
|
|
|
+ TAKEABORT;
|
|
|
+}
|
|
|
+
|
|
|
+/* This function does the Busy-Waiting for an MCR instruction. */
|
|
|
+
|
|
|
+void
|
|
|
+ARMul_MCR (ARMul_State * state, ARMword instr, ARMword source)
|
|
|
+{
|
|
|
+ unsigned cpab;
|
|
|
+
|
|
|
+ //printf("SKYEYE ARMul_MCR, CPnum is %x, source %x\n",CPNum, source);
|
|
|
+ if (!CP_ACCESS_ALLOWED (state, CPNum)) {
|
|
|
+ //chy 2004-07-19 should fix in the future ????!!!!
|
|
|
+ //printf("SKYEYE ARMul_MCR, ACCESS_not ALLOWed, UndefinedInstr CPnum is %x, source %x\n",CPNum, source);
|
|
|
+ ARMul_UndefInstr (state, instr);
|
|
|
+ return;
|
|
|
+ }
|
|
|
+
|
|
|
+ cpab = (state->MCR[CPNum]) (state, ARMul_FIRST, instr, source);
|
|
|
+
|
|
|
+ while (cpab == ARMul_BUSY) {
|
|
|
+ ARMul_Icycles (state, 1, 0);
|
|
|
+
|
|
|
+ if (IntPending (state)) {
|
|
|
+ cpab = (state->MCR[CPNum]) (state, ARMul_INTERRUPT,
|
|
|
+ instr, 0);
|
|
|
+ return;
|
|
|
+ }
|
|
|
+ else
|
|
|
+ cpab = (state->MCR[CPNum]) (state, ARMul_BUSY, instr,
|
|
|
+ source);
|
|
|
+ }
|
|
|
+
|
|
|
+ if (cpab == ARMul_CANT) {
|
|
|
+ printf ("SKYEYE ARMul_MCR, CANT, UndefinedInstr %x CPnum is %x, source %x\n", instr, CPNum, source);
|
|
|
+ ARMul_Abort (state, ARMul_UndefinedInstrV);
|
|
|
+ }
|
|
|
+ else {
|
|
|
+ BUSUSEDINCPCN;
|
|
|
+ ARMul_Ccycles (state, 1, 0);
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+/* This function does the Busy-Waiting for an MCRR instruction. */
|
|
|
+
|
|
|
+void
|
|
|
+ARMul_MCRR (ARMul_State * state, ARMword instr, ARMword source1, ARMword source2)
|
|
|
+{
|
|
|
+ unsigned cpab;
|
|
|
+
|
|
|
+ if (!CP_ACCESS_ALLOWED (state, CPNum)) {
|
|
|
+ ARMul_UndefInstr (state, instr);
|
|
|
+ return;
|
|
|
+ }
|
|
|
+
|
|
|
+ cpab = (state->MCRR[CPNum]) (state, ARMul_FIRST, instr, source1, source2);
|
|
|
+
|
|
|
+ while (cpab == ARMul_BUSY) {
|
|
|
+ ARMul_Icycles (state, 1, 0);
|
|
|
+
|
|
|
+ if (IntPending (state)) {
|
|
|
+ cpab = (state->MCRR[CPNum]) (state, ARMul_INTERRUPT,
|
|
|
+ instr, 0, 0);
|
|
|
+ return;
|
|
|
+ }
|
|
|
+ else
|
|
|
+ cpab = (state->MCRR[CPNum]) (state, ARMul_BUSY, instr,
|
|
|
+ source1, source2);
|
|
|
+ }
|
|
|
+ if (cpab == ARMul_CANT) {
|
|
|
+ printf ("In %s, CoProcesscor returned CANT, CPnum is %x, instr %x, source %x %x\n", __FUNCTION__, CPNum, instr, source1, source2);
|
|
|
+ ARMul_Abort (state, ARMul_UndefinedInstrV);
|
|
|
+ }
|
|
|
+ else {
|
|
|
+ BUSUSEDINCPCN;
|
|
|
+ ARMul_Ccycles (state, 1, 0);
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+/* This function does the Busy-Waiting for an MRC instruction. */
|
|
|
+
|
|
|
+ARMword
|
|
|
+ARMul_MRC (ARMul_State * state, ARMword instr)
|
|
|
+{
|
|
|
+ unsigned cpab;
|
|
|
+ ARMword result = 0;
|
|
|
+
|
|
|
+ //printf("SKYEYE ARMul_MRC, CPnum is %x, instr %x\n",CPNum, instr);
|
|
|
+ if (!CP_ACCESS_ALLOWED (state, CPNum)) {
|
|
|
+ //chy 2004-07-19 should fix in the future????!!!!
|
|
|
+ //printf("SKYEYE ARMul_MRC,NOT ALLOWed UndefInstr CPnum is %x, instr %x\n",CPNum, instr);
|
|
|
+ ARMul_UndefInstr (state, instr);
|
|
|
+ return -1;
|
|
|
+ }
|
|
|
+
|
|
|
+ cpab = (state->MRC[CPNum]) (state, ARMul_FIRST, instr, &result);
|
|
|
+ while (cpab == ARMul_BUSY) {
|
|
|
+ ARMul_Icycles (state, 1, 0);
|
|
|
+ if (IntPending (state)) {
|
|
|
+ cpab = (state->MRC[CPNum]) (state, ARMul_INTERRUPT,
|
|
|
+ instr, 0);
|
|
|
+ return (0);
|
|
|
+ }
|
|
|
+ else
|
|
|
+ cpab = (state->MRC[CPNum]) (state, ARMul_BUSY, instr,
|
|
|
+ &result);
|
|
|
+ }
|
|
|
+ if (cpab == ARMul_CANT) {
|
|
|
+ printf ("SKYEYE ARMul_MRC,CANT UndefInstr CPnum is %x, instr %x\n", CPNum, instr);
|
|
|
+ ARMul_Abort (state, ARMul_UndefinedInstrV);
|
|
|
+ /* Parent will destroy the flags otherwise. */
|
|
|
+ result = ECC;
|
|
|
+ }
|
|
|
+ else {
|
|
|
+ BUSUSEDINCPCN;
|
|
|
+ ARMul_Ccycles (state, 1, 0);
|
|
|
+ ARMul_Icycles (state, 1, 0);
|
|
|
+ }
|
|
|
+
|
|
|
+ return result;
|
|
|
+}
|
|
|
+
|
|
|
+/* This function does the Busy-Waiting for an MRRC instruction. (to verify) */
|
|
|
+
|
|
|
+void
|
|
|
+ARMul_MRRC (ARMul_State * state, ARMword instr, ARMword * dest1, ARMword * dest2)
|
|
|
+{
|
|
|
+ unsigned cpab;
|
|
|
+ ARMword result1 = 0;
|
|
|
+ ARMword result2 = 0;
|
|
|
+
|
|
|
+ if (!CP_ACCESS_ALLOWED (state, CPNum)) {
|
|
|
+ ARMul_UndefInstr (state, instr);
|
|
|
+ return;
|
|
|
+ }
|
|
|
+
|
|
|
+ cpab = (state->MRRC[CPNum]) (state, ARMul_FIRST, instr, &result1, &result2);
|
|
|
+ while (cpab == ARMul_BUSY) {
|
|
|
+ ARMul_Icycles (state, 1, 0);
|
|
|
+ if (IntPending (state)) {
|
|
|
+ cpab = (state->MRRC[CPNum]) (state, ARMul_INTERRUPT,
|
|
|
+ instr, 0, 0);
|
|
|
+ return;
|
|
|
+ }
|
|
|
+ else
|
|
|
+ cpab = (state->MRRC[CPNum]) (state, ARMul_BUSY, instr,
|
|
|
+ &result1, &result2);
|
|
|
+ }
|
|
|
+ if (cpab == ARMul_CANT) {
|
|
|
+ printf ("In %s, CoProcesscor returned CANT, CPnum is %x, instr %x\n", __FUNCTION__, CPNum, instr);
|
|
|
+ ARMul_Abort (state, ARMul_UndefinedInstrV);
|
|
|
+ }
|
|
|
+ else {
|
|
|
+ BUSUSEDINCPCN;
|
|
|
+ ARMul_Ccycles (state, 1, 0);
|
|
|
+ ARMul_Icycles (state, 1, 0);
|
|
|
+ }
|
|
|
+
|
|
|
+ *dest1 = result1;
|
|
|
+ *dest2 = result2;
|
|
|
+}
|
|
|
+
|
|
|
+/* This function does the Busy-Waiting for an CDP instruction. */
|
|
|
+
|
|
|
+void
|
|
|
+ARMul_CDP (ARMul_State * state, ARMword instr)
|
|
|
+{
|
|
|
+ unsigned cpab;
|
|
|
+
|
|
|
+ if (!CP_ACCESS_ALLOWED (state, CPNum)) {
|
|
|
+ ARMul_UndefInstr (state, instr);
|
|
|
+ return;
|
|
|
+ }
|
|
|
+ cpab = (state->CDP[CPNum]) (state, ARMul_FIRST, instr);
|
|
|
+ while (cpab == ARMul_BUSY) {
|
|
|
+ ARMul_Icycles (state, 1, 0);
|
|
|
+ if (IntPending (state)) {
|
|
|
+ cpab = (state->CDP[CPNum]) (state, ARMul_INTERRUPT,
|
|
|
+ instr);
|
|
|
+ return;
|
|
|
+ }
|
|
|
+ else
|
|
|
+ cpab = (state->CDP[CPNum]) (state, ARMul_BUSY, instr);
|
|
|
+ }
|
|
|
+ if (cpab == ARMul_CANT)
|
|
|
+ ARMul_Abort (state, ARMul_UndefinedInstrV);
|
|
|
+ else
|
|
|
+ BUSUSEDN;
|
|
|
+}
|
|
|
+
|
|
|
+/* This function handles Undefined instructions, as CP isntruction. */
|
|
|
+
|
|
|
+void
|
|
|
+ARMul_UndefInstr (ARMul_State * state, ARMword instr)
|
|
|
+{
|
|
|
+ ERROR_LOG(ARM11, "Undefined instruction!! Instr: 0x%x", instr);
|
|
|
+ ARMul_Abort (state, ARMul_UndefinedInstrV);
|
|
|
+}
|
|
|
+
|
|
|
+/* Return TRUE if an interrupt is pending, FALSE otherwise. */
|
|
|
+
|
|
|
+unsigned
|
|
|
+IntPending (ARMul_State * state)
|
|
|
+{
|
|
|
+ /* Any exceptions. */
|
|
|
+ if (state->NresetSig == LOW) {
|
|
|
+ ARMul_Abort (state, ARMul_ResetV);
|
|
|
+ return TRUE;
|
|
|
+ }
|
|
|
+ else if (!state->NfiqSig && !FFLAG) {
|
|
|
+ ARMul_Abort (state, ARMul_FIQV);
|
|
|
+ return TRUE;
|
|
|
+ }
|
|
|
+ else if (!state->NirqSig && !IFLAG) {
|
|
|
+ ARMul_Abort (state, ARMul_IRQV);
|
|
|
+ return TRUE;
|
|
|
+ }
|
|
|
+
|
|
|
+ return FALSE;
|
|
|
+}
|
|
|
+
|
|
|
+/* Align a word access to a non word boundary. */
|
|
|
+
|
|
|
+ARMword
|
|
|
+ARMul_Align (ARMul_State *state, ARMword address, ARMword data)
|
|
|
+{
|
|
|
+ /* This code assumes the address is really unaligned,
|
|
|
+ as a shift by 32 is undefined in C. */
|
|
|
+
|
|
|
+ address = (address & 3) << 3; /* Get the word address. */
|
|
|
+ return ((data >> address) | (data << (32 - address))); /* rot right */
|
|
|
+}
|
|
|
+
|
|
|
+/* This routine is used to call another routine after a certain number of
|
|
|
+ cycles have been executed. The first parameter is the number of cycles
|
|
|
+ delay before the function is called, the second argument is a pointer
|
|
|
+ to the function. A delay of zero doesn't work, just call the function. */
|
|
|
+
|
|
|
+void
|
|
|
+ARMul_ScheduleEvent (ARMul_State * state, unsigned int delay,
|
|
|
+ unsigned (*what) (ARMul_State *))
|
|
|
+{
|
|
|
+ unsigned int when;
|
|
|
+ struct EventNode *event;
|
|
|
+
|
|
|
+ if (state->EventSet++ == 0)
|
|
|
+ state->Now = ARMul_Time (state);
|
|
|
+ when = (state->Now + delay) % EVENTLISTSIZE;
|
|
|
+ event = (struct EventNode *) malloc (sizeof (struct EventNode));
|
|
|
+
|
|
|
+ _dbg_assert_msg_(ARM11, event, "SKYEYE:ARMul_ScheduleEvent: malloc event error\n");
|
|
|
+
|
|
|
+ event->func = what;
|
|
|
+ event->next = *(state->EventPtr + when);
|
|
|
+ *(state->EventPtr + when) = event;
|
|
|
+}
|
|
|
+
|
|
|
+/* This routine is called at the beginning of
|
|
|
+ every cycle, to envoke scheduled events. */
|
|
|
+
|
|
|
+void
|
|
|
+ARMul_EnvokeEvent (ARMul_State * state)
|
|
|
+{
|
|
|
+ static unsigned int then;
|
|
|
+
|
|
|
+ then = state->Now;
|
|
|
+ state->Now = ARMul_Time (state) % EVENTLISTSIZE;
|
|
|
+ if (then < state->Now)
|
|
|
+ /* Schedule events. */
|
|
|
+ EnvokeList (state, then, state->Now);
|
|
|
+ else if (then > state->Now) {
|
|
|
+ /* Need to wrap around the list. */
|
|
|
+ EnvokeList (state, then, EVENTLISTSIZE - 1L);
|
|
|
+ EnvokeList (state, 0L, state->Now);
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+/* Envokes all the entries in a range. */
|
|
|
+
|
|
|
+static void
|
|
|
+EnvokeList (ARMul_State * state, unsigned int from, unsigned int to)
|
|
|
+{
|
|
|
+ for (; from <= to; from++) {
|
|
|
+ struct EventNode *anevent;
|
|
|
+
|
|
|
+ anevent = *(state->EventPtr + from);
|
|
|
+ while (anevent) {
|
|
|
+ (anevent->func) (state);
|
|
|
+ state->EventSet--;
|
|
|
+ anevent = anevent->next;
|
|
|
+ }
|
|
|
+ *(state->EventPtr + from) = NULL;
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+/* This routine is returns the number of clock ticks since the last reset. */
|
|
|
+
|
|
|
+unsigned int
|
|
|
+ARMul_Time (ARMul_State * state)
|
|
|
+{
|
|
|
+ return (state->NumScycles + state->NumNcycles +
|
|
|
+ state->NumIcycles + state->NumCcycles + state->NumFcycles);
|
|
|
+}
|
bunnei