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@@ -6496,58 +6496,33 @@ L_stm_s_takeabort:
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return 1;
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}
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- case 0x6f: {
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- ARMword Rm;
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- int ror = -1;
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-
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- switch (BITS(4, 11)) {
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- case 0x07:
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- ror = 0;
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- break;
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- case 0x47:
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- ror = 8;
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- break;
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- case 0x87:
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- ror = 16;
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- break;
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- case 0xc7:
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- ror = 24;
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- break;
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+ case 0x6f: // UXTH, UXTAH, and REVSH.
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+ {
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+ const u8 op2 = BITS(5, 7);
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- case 0xfb: // REVSH
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- {
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- DEST = ((RHS & 0xFF) << 8) | ((RHS & 0xFF00) >> 8);
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- if (DEST & 0x8000)
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- DEST |= 0xffff0000;
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- return 1;
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- }
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- default:
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- break;
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+ // REVSH
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+ if (op2 == 0x05) {
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+ DEST = ((RHS & 0xFF) << 8) | ((RHS & 0xFF00) >> 8);
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+ if (DEST & 0x8000)
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+ DEST |= 0xffff0000;
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+ return 1;
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}
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+ // UXTH and UXTAH
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+ else if (op2 == 0x03) {
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+ const u8 rotate = BITS(10, 11) * 8;
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+ const ARMword rm = ((state->Reg[BITS(0, 3)] >> rotate) & 0xFFFF) | (((state->Reg[BITS(0, 3)] << (32 - rotate)) & 0xFFFF) & 0xFFFF);
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+
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+ // UXTH
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+ if (BITS(16, 19) == 0xf) {
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+ state->Reg[BITS(12, 15)] = rm;
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+ }
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+ // UXTAH
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+ else {
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+ state->Reg[BITS(12, 15)] = state->Reg[BITS(16, 19)] + rm;
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+ }
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- if (ror == -1)
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- break;
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-
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- Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFFFF) | (((state->Reg[BITS(0, 3)] << (32 - ror)) & 0xFFFF) & 0xFFFF);
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-
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- /* UXT */
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- /* state->Reg[BITS (12, 15)] = Rm; */
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- /* dyf add */
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- if (BITS(16, 19) == 0xf) {
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- state->Reg[BITS(12, 15)] = Rm;
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- }
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- else {
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- /* UXTAH */
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- /* state->Reg[BITS (12, 15)] = state->Reg [BITS (16, 19)] + Rm; */
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- // printf("rd is %x rn is %x rm is %x rotate is %x\n", state->Reg[BITS (12, 15)], state->Reg[BITS (16, 19)]
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- // , Rm, BITS(10, 11));
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- // printf("icounter is %lld\n", state->NumInstrs);
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- state->Reg[BITS(12, 15)] = state->Reg[BITS(16, 19)] + Rm;
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- // printf("rd is %x\n", state->Reg[BITS (12, 15)]);
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- // exit(-1);
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+ return 1;
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}
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-
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- return 1;
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}
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case 0x70:
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// ichfly
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