shader: Implement LEA

src/shader_recompiler/CMakeLists.txt

@@ -86,6 +86,7 @@ add_library(shader_recompiler STATIC
     frontend/maxwell/translate/impl/integer_shift_right.cpp
     frontend/maxwell/translate/impl/integer_short_multiply_add.cpp
     frontend/maxwell/translate/impl/integer_to_integer_conversion.cpp
+    frontend/maxwell/translate/impl/load_effective_address.cpp
     frontend/maxwell/translate/impl/load_store_attribute.cpp
     frontend/maxwell/translate/impl/load_store_memory.cpp
     frontend/maxwell/translate/impl/logic_operation.cpp

src/shader_recompiler/backend/spirv/emit_spirv.h

@@ -132,7 +132,7 @@ void EmitBitCastU64F64(EmitContext& ctx);
 void EmitBitCastF16U16(EmitContext& ctx);
 Id EmitBitCastF32U32(EmitContext& ctx, Id value);
 void EmitBitCastF64U64(EmitContext& ctx);
-void EmitPackUint2x32(EmitContext& ctx);
+Id EmitPackUint2x32(EmitContext& ctx, Id value);
 Id EmitUnpackUint2x32(EmitContext& ctx, Id value);
 Id EmitPackFloat2x16(EmitContext& ctx, Id value);
 Id EmitUnpackFloat2x16(EmitContext& ctx, Id value);
@@ -229,9 +229,11 @@ Id EmitISub32(EmitContext& ctx, Id a, Id b);
 void EmitISub64(EmitContext& ctx);
 Id EmitIMul32(EmitContext& ctx, Id a, Id b);
 Id EmitINeg32(EmitContext& ctx, Id value);
+Id EmitINeg64(EmitContext& ctx, Id value);
 Id EmitIAbs32(EmitContext& ctx, Id value);
 Id EmitShiftLeftLogical32(EmitContext& ctx, Id base, Id shift);
 Id EmitShiftRightLogical32(EmitContext& ctx, Id a, Id b);
+Id EmitShiftRightLogical64(EmitContext& ctx, Id a, Id b);
 Id EmitShiftRightArithmetic32(EmitContext& ctx, Id a, Id b);
 Id EmitBitwiseAnd32(EmitContext& ctx, Id a, Id b);
 Id EmitBitwiseOr32(EmitContext& ctx, Id a, Id b);

src/shader_recompiler/backend/spirv/emit_spirv_bitwise_conversion.cpp

@@ -30,8 +30,8 @@ void EmitBitCastF64U64(EmitContext&) {
     throw NotImplementedException("SPIR-V Instruction");
 }
 
-void EmitPackUint2x32(EmitContext&) {
-    throw NotImplementedException("SPIR-V Instruction");
+Id EmitPackUint2x32(EmitContext& ctx, Id value) {
+    return ctx.OpBitcast(ctx.U64, value);
 }
 
 Id EmitUnpackUint2x32(EmitContext& ctx, Id value) {

src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp

@@ -62,6 +62,10 @@ Id EmitINeg32(EmitContext& ctx, Id value) {
     return ctx.OpSNegate(ctx.U32[1], value);
 }
 
+Id EmitINeg64(EmitContext& ctx, Id value) {
+    return ctx.OpSNegate(ctx.U64, value);
+}
+
 Id EmitIAbs32(EmitContext& ctx, Id value) {
     return ctx.OpSAbs(ctx.U32[1], value);
 }
@@ -74,6 +78,10 @@ Id EmitShiftRightLogical32(EmitContext& ctx, Id a, Id b) {
     return ctx.OpShiftRightLogical(ctx.U32[1], a, b);
 }
 
+Id EmitShiftRightLogical64(EmitContext& ctx, Id a, Id b) {
+    return ctx.OpShiftRightLogical(ctx.U64, a, b);
+}
+
 Id EmitShiftRightArithmetic32(EmitContext& ctx, Id a, Id b) {
     return ctx.OpShiftRightArithmetic(ctx.U32[1], a, b);
 }

src/shader_recompiler/frontend/ir/ir_emitter.cpp

@@ -798,8 +798,15 @@ U32 IREmitter::IMul(const U32& a, const U32& b) {
     return Inst<U32>(Opcode::IMul32, a, b);
 }
 
-U32 IREmitter::INeg(const U32& value) {
-    return Inst<U32>(Opcode::INeg32, value);
+U32U64 IREmitter::INeg(const U32U64& value) {
+    switch (value.Type()) {
+    case Type::U32:
+        return Inst<U32>(Opcode::INeg32, value);
+    case Type::U64:
+        return Inst<U64>(Opcode::INeg64, value);
+    default:
+        ThrowInvalidType(value.Type());
+    }
 }
 
 U32 IREmitter::IAbs(const U32& value) {
@@ -810,8 +817,15 @@ U32 IREmitter::ShiftLeftLogical(const U32& base, const U32& shift) {
     return Inst<U32>(Opcode::ShiftLeftLogical32, base, shift);
 }
 
-U32 IREmitter::ShiftRightLogical(const U32& base, const U32& shift) {
-    return Inst<U32>(Opcode::ShiftRightLogical32, base, shift);
+U32U64 IREmitter::ShiftRightLogical(const U32U64& base, const U32& shift) {
+    switch (base.Type()) {
+    case Type::U32:
+        return Inst<U32>(Opcode::ShiftRightLogical32, base, shift);
+    case Type::U64:
+        return Inst<U64>(Opcode::ShiftRightLogical64, base, shift);
+    default:
+        ThrowInvalidType(base.Type());
+    }
 }
 
 U32 IREmitter::ShiftRightArithmetic(const U32& base, const U32& shift) {

src/shader_recompiler/frontend/ir/ir_emitter.h

@@ -148,10 +148,10 @@ public:
     [[nodiscard]] U32U64 IAdd(const U32U64& a, const U32U64& b);
     [[nodiscard]] U32U64 ISub(const U32U64& a, const U32U64& b);
     [[nodiscard]] U32 IMul(const U32& a, const U32& b);
-    [[nodiscard]] U32 INeg(const U32& value);
+    [[nodiscard]] U32U64 INeg(const U32U64& value);
     [[nodiscard]] U32 IAbs(const U32& value);
     [[nodiscard]] U32 ShiftLeftLogical(const U32& base, const U32& shift);
-    [[nodiscard]] U32 ShiftRightLogical(const U32& base, const U32& shift);
+    [[nodiscard]] U32U64 ShiftRightLogical(const U32U64& base, const U32& shift);
     [[nodiscard]] U32 ShiftRightArithmetic(const U32& base, const U32& shift);
     [[nodiscard]] U32 BitwiseAnd(const U32& a, const U32& b);
     [[nodiscard]] U32 BitwiseOr(const U32& a, const U32& b);

src/shader_recompiler/frontend/ir/opcodes.inc

@@ -233,9 +233,11 @@ OPCODE(ISub32,                                              U32,            U32,
 OPCODE(ISub64,                                              U64,            U64,            U64,                                            )
 OPCODE(IMul32,                                              U32,            U32,            U32,                                            )
 OPCODE(INeg32,                                              U32,            U32,                                                            )
+OPCODE(INeg64,                                              U64,            U64,                                                            )
 OPCODE(IAbs32,                                              U32,            U32,                                                            )
 OPCODE(ShiftLeftLogical32,                                  U32,            U32,            U32,                                            )
 OPCODE(ShiftRightLogical32,                                 U32,            U32,            U32,                                            )
+OPCODE(ShiftRightLogical64,                                 U64,            U64,            U32,                                            )
 OPCODE(ShiftRightArithmetic32,                              U32,            U32,            U32,                                            )
 OPCODE(BitwiseAnd32,                                        U32,            U32,            U32,                                            )
 OPCODE(BitwiseOr32,                                         U32,            U32,            U32,                                            )

src/shader_recompiler/frontend/maxwell/translate/impl/load_effective_address.cpp

@@ -0,0 +1,100 @@
+// Copyright 2021 yuzu Emulator Project
+// Licensed under GPLv2 or any later version
+// Refer to the license.txt file included.
+
+#include "common/bit_field.h"
+#include "common/common_types.h"
+#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
+
+namespace Shader::Maxwell {
+namespace {
+void LEA_hi(TranslatorVisitor& v, u64 insn, const IR::U32& base, IR::U32 offset_hi, u64 scale,
+            bool neg, bool x) {
+    union {
+        u64 insn;
+        BitField<0, 8, IR::Reg> dest_reg;
+        BitField<8, 8, IR::Reg> offset_lo_reg;
+        BitField<48, 3, IR::Pred> pred;
+    } const lea{insn};
+
+    if (x) {
+        throw NotImplementedException("LEA.HI X");
+    }
+    if (lea.pred != IR::Pred::PT) {
+        throw NotImplementedException("LEA.LO Pred");
+    }
+
+    const IR::U32 offset_lo{v.X(lea.offset_lo_reg)};
+    const IR::U64 packed_offset{v.ir.PackUint2x32(v.ir.CompositeConstruct(offset_lo, offset_hi))};
+    const IR::U64 offset{neg ? IR::U64{v.ir.INeg(packed_offset)} : packed_offset};
+
+    const s32 hi_scale{32 - static_cast<s32>(scale)};
+    const IR::U64 scaled_offset{v.ir.ShiftRightLogical(offset, v.ir.Imm32(hi_scale))};
+    const IR::U32 scaled_offset_w0{v.ir.CompositeExtract(v.ir.UnpackUint2x32(scaled_offset), 0)};
+
+    IR::U32 result{v.ir.IAdd(base, scaled_offset_w0)};
+    v.X(lea.dest_reg, result);
+}
+
+void LEA_lo(TranslatorVisitor& v, u64 insn, const IR::U32& base) {
+    union {
+        u64 insn;
+        BitField<0, 8, IR::Reg> dest_reg;
+        BitField<8, 8, IR::Reg> offset_lo_reg;
+        BitField<39, 5, u64> scale;
+        BitField<45, 1, u64> neg;
+        BitField<46, 1, u64> x;
+        BitField<48, 3, IR::Pred> pred;
+    } const lea{insn};
+    if (lea.x != 0) {
+        throw NotImplementedException("LEA.LO X");
+    }
+    if (lea.pred != IR::Pred::PT) {
+        throw NotImplementedException("LEA.LO Pred");
+    }
+
+    const IR::U32 offset_lo{v.X(lea.offset_lo_reg)};
+    const s32 scale{static_cast<s32>(lea.scale)};
+    const IR::U32 offset{lea.neg != 0 ? IR::U32{v.ir.INeg(offset_lo)} : offset_lo};
+    const IR::U32 scaled_offset{v.ir.ShiftLeftLogical(offset, v.ir.Imm32(scale))};
+
+    IR::U32 result{v.ir.IAdd(base, scaled_offset)};
+    v.X(lea.dest_reg, result);
+}
+} // Anonymous namespace
+
+void TranslatorVisitor::LEA_hi_reg(u64 insn) {
+    union {
+        u64 insn;
+        BitField<28, 5, u64> scale;
+        BitField<37, 1, u64> neg;
+        BitField<38, 1, u64> x;
+    } const lea{insn};
+
+    LEA_hi(*this, insn, GetReg20(insn), GetReg39(insn), lea.scale, lea.neg != 0, lea.x != 0);
+}
+
+void TranslatorVisitor::LEA_hi_cbuf(u64 insn) {
+    union {
+        u64 insn;
+        BitField<51, 5, u64> scale;
+        BitField<56, 1, u64> neg;
+        BitField<57, 1, u64> x;
+    } const lea{insn};
+
+    LEA_hi(*this, insn, GetCbuf(insn), GetReg39(insn), lea.scale, lea.neg != 0, lea.x != 0);
+}
+
+void TranslatorVisitor::LEA_lo_reg(u64 insn) {
+    LEA_lo(*this, insn, GetReg20(insn));
+}
+
+void TranslatorVisitor::LEA_lo_cbuf(u64 insn) {
+    LEA_lo(*this, insn, GetCbuf(insn));
+}
+
+void TranslatorVisitor::LEA_lo_imm(u64 insn) {
+    LEA_lo(*this, insn, GetImm20(insn));
+}
+
+} // namespace Shader::Maxwell

src/shader_recompiler/frontend/maxwell/translate/impl/not_implemented.cpp

@@ -437,26 +437,6 @@ void TranslatorVisitor::LDS(u64) {
     ThrowNotImplemented(Opcode::LDS);
 }
 
-void TranslatorVisitor::LEA_hi_reg(u64) {
-    ThrowNotImplemented(Opcode::LEA_hi_reg);
-}
-
-void TranslatorVisitor::LEA_hi_cbuf(u64) {
-    ThrowNotImplemented(Opcode::LEA_hi_cbuf);
-}
-
-void TranslatorVisitor::LEA_lo_reg(u64) {
-    ThrowNotImplemented(Opcode::LEA_lo_reg);
-}
-
-void TranslatorVisitor::LEA_lo_cbuf(u64) {
-    ThrowNotImplemented(Opcode::LEA_lo_cbuf);
-}
-
-void TranslatorVisitor::LEA_lo_imm(u64) {
-    ThrowNotImplemented(Opcode::LEA_lo_imm);
-}
-
 void TranslatorVisitor::LEPC(u64) {
     ThrowNotImplemented(Opcode::LEPC);
 }