Merge pull request #335 from lioncash/cpsrcreate

armemu: Emulate the GE and Q flags.

src/core/arm/interpreter/armemu.cpp

@@ -5877,6 +5877,8 @@ L_stm_s_takeabort:
                     state->Cpsr &= ~(1 << 18);
                     state->Cpsr &= ~(1 << 19);
                 }
+
+                ARMul_CPSRAltered(state);
                 return 1;
             }
             // SADD8/SSUB8
@@ -5948,6 +5950,7 @@ L_stm_s_takeabort:
                         state->Cpsr &= ~(1 << 19);
                 }
 
+                ARMul_CPSRAltered(state);
                 state->Reg[rd_idx] = (lo_val1 | lo_val2 << 8 | hi_val1 << 16 | hi_val2 << 24);
                 return 1;
             }
@@ -6024,15 +6027,33 @@ L_stm_s_takeabort:
                 if ((instr & 0x0F0) == 0x070) { // USUB16
                     h1 = ((u16)from - (u16)to);
                     h2 = ((u16)(from >> 16) - (u16)(to >> 16));
-                    if (!(h1 & 0xffff0000)) state->Cpsr |= (3 << 16);
-                    if (!(h2 & 0xffff0000)) state->Cpsr |= (3 << 18);
+
+                    if (!(h1 & 0xffff0000))
+                        state->Cpsr |= (3 << 16);
+                    else
+                        state->Cpsr &= ~(3 << 16);
+
+                    if (!(h2 & 0xffff0000))
+                        state->Cpsr |= (3 << 18);
+                    else
+                        state->Cpsr &= ~(3 << 18);
                 }
                 else { // UADD16
                     h1 = ((u16)from + (u16)to);
                     h2 = ((u16)(from >> 16) + (u16)(to >> 16));
-                    if (h1 & 0xffff0000) state->Cpsr |= (3 << 16);
-                    if (h2 & 0xffff0000) state->Cpsr |= (3 << 18);
+
+                    if (h1 & 0xffff0000)
+                        state->Cpsr |= (3 << 16);
+                    else
+                        state->Cpsr &= ~(3 << 16);
+
+                    if (h2 & 0xffff0000)
+                        state->Cpsr |= (3 << 18);
+                    else
+                        state->Cpsr &= ~(3 << 18);
                 }
+
+                ARMul_CPSRAltered(state);
                 state->Reg[rd] = (u32)((h1 & 0xffff) | ((h2 & 0xffff) << 16));
                 return 1;
             }
@@ -6045,10 +6066,26 @@ L_stm_s_takeabort:
                         b2 = ((u8)(from >> 8) - (u8)(to >> 8));
                         b3 = ((u8)(from >> 16) - (u8)(to >> 16));
                         b4 = ((u8)(from >> 24) - (u8)(to >> 24));
-                        if (!(b1 & 0xffffff00)) state->Cpsr |= (1 << 16);
-                        if (!(b2 & 0xffffff00)) state->Cpsr |= (1 << 17);
-                        if (!(b3 & 0xffffff00)) state->Cpsr |= (1 << 18);
-                        if (!(b4 & 0xffffff00)) state->Cpsr |= (1 << 19);
+
+                        if (!(b1 & 0xffffff00))
+                            state->Cpsr |= (1 << 16);
+                        else
+                            state->Cpsr &= ~(1 << 16);
+
+                        if (!(b2 & 0xffffff00))
+                            state->Cpsr |= (1 << 17);
+                        else
+                            state->Cpsr &= ~(1 << 17);
+
+                        if (!(b3 & 0xffffff00))
+                            state->Cpsr |= (1 << 18);
+                        else
+                            state->Cpsr &= ~(1 << 18);
+
+                        if (!(b4 & 0xffffff00))
+                            state->Cpsr |= (1 << 19);
+                        else
+                            state->Cpsr &= ~(1 << 19);
                     }
                     else { // UADD8
                         b1 = ((u8)from + (u8)to);
@@ -6071,13 +6108,13 @@ L_stm_s_takeabort:
                         else
                             state->Cpsr &= ~(1 << 18);
 
-
                         if (b4 & 0xffffff00)
                             state->Cpsr |= (1 << 19);
                         else
                             state->Cpsr &= ~(1 << 19);
                     }
 
+                    ARMul_CPSRAltered(state);
                     state->Reg[rd] = (u32)(b1 | (b2 & 0xff) << 8 | (b3 & 0xff) << 16 | (b4 & 0xff) << 24);
                     return 1;
                 }
@@ -6116,7 +6153,7 @@ L_stm_s_takeabort:
             u32 rm = (instr >> 0) & 0xF;
             u32 from = state->Reg[rn];
             u32 to = state->Reg[rm];
-            u32 cpsr = state->Cpsr;
+            u32 cpsr = ARMul_GetCPSR(state);
             if ((instr & 0xFF0) == 0xFB0) { // SEL
                 u32 result;
                 if (cpsr & (1 << 16))
@@ -6172,16 +6209,23 @@ L_stm_s_takeabort:
 					s16 rn_lo = (state->Reg[rn_idx]);
 					s16 rn_hi = (state->Reg[rn_idx] >> 16);
 
-					if (rn_lo > max)
+					if (rn_lo > max) {
 						rn_lo = max;
-					else if (rn_lo < min)
+						state->Cpsr |= (1 << 27);
+					} else if (rn_lo < min) {
 						rn_lo = min;
+						state->Cpsr |= (1 << 27);
+					}
 
-					if (rn_hi > max)
+					if (rn_hi > max) {
 						rn_hi = max;
-					else if (rn_hi < min)
+						state->Cpsr |= (1 << 27);
+					} else if (rn_hi < min) {
 						rn_hi = min;
+						state->Cpsr |= (1 << 27);
+					}
 
+					ARMul_CPSRAltered(state);
 					state->Reg[rd_idx] = (rn_lo & 0xFFFF) | ((rn_hi & 0xFFFF) << 16);
 					return 1;
 				}
@@ -6313,16 +6357,23 @@ L_stm_s_takeabort:
 					s16 rn_lo = (state->Reg[rn_idx]);
 					s16 rn_hi = (state->Reg[rn_idx] >> 16);
 					
-					if (max < rn_lo)
+					if (max < rn_lo) {
 						rn_lo = max;
-					else if (rn_lo < 0)
+						state->Cpsr |= (1 << 27);
+					} else if (rn_lo < 0) {
 						rn_lo = 0;
+						state->Cpsr |= (1 << 27);
+					}
 
-					if (max < rn_hi)
+					if (max < rn_hi) {
 						rn_hi = max;
-					else if (rn_hi < 0)
+						state->Cpsr |= (1 << 27);
+					} else if (rn_hi < 0) {
 						rn_hi = 0;
-					
+						state->Cpsr |= (1 << 27);
+					}
+
+					ARMul_CPSRAltered(state);
 					state->Reg[rd_idx] = (rn_lo & 0xFFFF) | ((rn_hi << 16) & 0xFFFF);
 					return 1;
 				}

src/core/arm/interpreter/armsupp.cpp

@@ -227,8 +227,9 @@ ARMul_CPSRAltered (ARMul_State * state)
     //state->Cpsr &= ~CBIT;
     ASSIGNV ((state->Cpsr & VBIT) != 0);
     //state->Cpsr &= ~VBIT;
-    ASSIGNS ((state->Cpsr & SBIT) != 0);
-    //state->Cpsr &= ~SBIT;
+    ASSIGNQ ((state->Cpsr & QBIT) != 0);
+    //state->Cpsr &= ~QBIT;
+    state->GEFlag = (state->Cpsr & 0x000F0000);
 #ifdef MODET
     ASSIGNT ((state->Cpsr & TBIT) != 0);
     //state->Cpsr &= ~TBIT;

src/core/arm/skyeye_common/armdefs.h

@@ -198,7 +198,7 @@ struct ARMul_State
         //ARMword translate_pc;
 
     /* add armv6 flags dyf:2010-08-09 */
-    ARMword GEFlag, EFlag, AFlag, QFlags;
+    ARMword GEFlag, EFlag, AFlag, QFlag;
     //chy:2003-08-19, used in arm v5e|xscale
     ARMword SFlag;
 #ifdef MODET

src/core/arm/skyeye_common/armemu.h

@@ -34,7 +34,7 @@
 #define ZBIT (1L << 30)
 #define CBIT (1L << 29)
 #define VBIT (1L << 28)
-#define SBIT (1L << 27)
+#define QBIT (1L << 27)
 #define IBIT (1L << 7)
 #define FBIT (1L << 6)
 #define IFBITS (3L << 6)
@@ -156,13 +156,14 @@
 #define R15PCMODE (state->Reg[15] & (R15PCBITS | R15MODEBITS))
 #define R15MODE (state->Reg[15] & R15MODEBITS)
 
-#define ECC ((NFLAG << 31) | (ZFLAG << 30) | (CFLAG << 29) | (VFLAG << 28) | (SFLAG << 27))
+#define ECC ((NFLAG << 31) | (ZFLAG << 30) | (CFLAG << 29) | (VFLAG << 28) | (QFLAG << 27))
 #define EINT (IFFLAGS << 6)
 #define ER15INT (IFFLAGS << 26)
 #define EMODE (state->Mode)
+#define EGEBITS (state->GEFlag & 0x000F0000)
 
 #ifdef MODET
-#define CPSR (ECC | EINT | EMODE | (TFLAG << 5))
+#define CPSR (ECC | EGEBITS | (EFLAG << 9) | (AFLAG << 8) | EINT | (TFLAG << 5) | EMODE)
 #else
 #define CPSR (ECC | EINT | EMODE)
 #endif