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@@ -89,7 +89,7 @@
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#endif
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//#define DBCT_TEST_SPEED
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-#define DBCT_TEST_SPEED_SEC 10
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+#define DBCT_TEST_SPEED_SEC 10
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//AJ2D--------------------------------------------------------------------------
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//teawater add compile switch for DBCT GDB RSP function 2005.10.21--------------
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@@ -99,9 +99,9 @@
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//#include <skyeye_defs.h>
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//#include <skyeye_types.h>
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-#define ARM_BYTE_TYPE 0
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-#define ARM_HALFWORD_TYPE 1
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-#define ARM_WORD_TYPE 2
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+#define ARM_BYTE_TYPE 0
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+#define ARM_HALFWORD_TYPE 1
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+#define ARM_WORD_TYPE 2
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//the define of cachetype
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#define NONCACHE 0
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@@ -112,10 +112,10 @@
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typedef char *VoidStar;
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#endif
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-typedef unsigned long long ARMdword; /* must be 64 bits wide */
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-typedef unsigned int ARMword; /* must be 32 bits wide */
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-typedef unsigned char ARMbyte; /* must be 8 bits wide */
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-typedef unsigned short ARMhword; /* must be 16 bits wide */
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+typedef unsigned long long ARMdword; /* must be 64 bits wide */
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+typedef unsigned int ARMword; /* must be 32 bits wide */
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+typedef unsigned char ARMbyte; /* must be 8 bits wide */
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+typedef unsigned short ARMhword; /* must be 16 bits wide */
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typedef struct ARMul_State ARMul_State;
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typedef struct ARMul_io ARMul_io;
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typedef struct ARMul_Energy ARMul_Energy;
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@@ -152,59 +152,59 @@ typedef unsigned long long uint64_t;
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typedef unsigned ARMul_CPInits (ARMul_State * state);
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typedef unsigned ARMul_CPExits (ARMul_State * state);
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typedef unsigned ARMul_LDCs (ARMul_State * state, unsigned type,
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- ARMword instr, ARMword value);
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+ ARMword instr, ARMword value);
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typedef unsigned ARMul_STCs (ARMul_State * state, unsigned type,
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- ARMword instr, ARMword * value);
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+ ARMword instr, ARMword * value);
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typedef unsigned ARMul_MRCs (ARMul_State * state, unsigned type,
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- ARMword instr, ARMword * value);
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+ ARMword instr, ARMword * value);
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typedef unsigned ARMul_MCRs (ARMul_State * state, unsigned type,
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- ARMword instr, ARMword value);
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+ ARMword instr, ARMword value);
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typedef unsigned ARMul_MRRCs (ARMul_State * state, unsigned type,
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- ARMword instr, ARMword * value1, ARMword * value2);
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+ ARMword instr, ARMword * value1, ARMword * value2);
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typedef unsigned ARMul_MCRRs (ARMul_State * state, unsigned type,
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- ARMword instr, ARMword value1, ARMword value2);
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+ ARMword instr, ARMword value1, ARMword value2);
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typedef unsigned ARMul_CDPs (ARMul_State * state, unsigned type,
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- ARMword instr);
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+ ARMword instr);
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typedef unsigned ARMul_CPReads (ARMul_State * state, unsigned reg,
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- ARMword * value);
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+ ARMword * value);
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typedef unsigned ARMul_CPWrites (ARMul_State * state, unsigned reg,
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- ARMword value);
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+ ARMword value);
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//added by ksh,2004-3-5
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struct ARMul_io
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{
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- ARMword *instr; //to display the current interrupt state
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- ARMword *net_flag; //to judge if network is enabled
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- ARMword *net_int; //netcard interrupt
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-
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- //ywc,2004-04-01
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- ARMword *ts_int;
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- ARMword *ts_is_enable;
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- ARMword *ts_addr_begin;
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- ARMword *ts_addr_end;
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- ARMword *ts_buffer;
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+ ARMword *instr; //to display the current interrupt state
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+ ARMword *net_flag; //to judge if network is enabled
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+ ARMword *net_int; //netcard interrupt
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+
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+ //ywc,2004-04-01
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+ ARMword *ts_int;
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+ ARMword *ts_is_enable;
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+ ARMword *ts_addr_begin;
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+ ARMword *ts_addr_end;
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+ ARMword *ts_buffer;
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};
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/* added by ksh,2004-11-26,some energy profiling */
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struct ARMul_Energy
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{
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- int energy_prof; /* <tktan> BUG200103282109 : for energy profiling */
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- int enable_func_energy; /* <tktan> BUG200105181702 */
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- char *func_energy;
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- int func_display; /* <tktan> BUG200103311509 : for function call display */
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- int func_disp_start; /* <tktan> BUG200104191428 : to start func profiling */
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- char *start_func; /* <tktan> BUG200104191428 */
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-
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- FILE *outfile; /* <tktan> BUG200105201531 : direct console to file */
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- long long tcycle, pcycle;
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- float t_energy;
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- void *cur_task; /* <tktan> BUG200103291737 */
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- long long t_mem_cycle, t_idle_cycle, t_uart_cycle;
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- long long p_mem_cycle, p_idle_cycle, p_uart_cycle;
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- long long p_io_update_tcycle;
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- /*record CCCR,to get current core frequency */
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- ARMword cccr;
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+ int energy_prof; /* <tktan> BUG200103282109 : for energy profiling */
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+ int enable_func_energy; /* <tktan> BUG200105181702 */
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+ char *func_energy;
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+ int func_display; /* <tktan> BUG200103311509 : for function call display */
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+ int func_disp_start; /* <tktan> BUG200104191428 : to start func profiling */
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+ char *start_func; /* <tktan> BUG200104191428 */
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+
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+ FILE *outfile; /* <tktan> BUG200105201531 : direct console to file */
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+ long long tcycle, pcycle;
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+ float t_energy;
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+ void *cur_task; /* <tktan> BUG200103291737 */
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+ long long t_mem_cycle, t_idle_cycle, t_uart_cycle;
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+ long long p_mem_cycle, p_idle_cycle, p_uart_cycle;
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+ long long p_io_update_tcycle;
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+ /*record CCCR,to get current core frequency */
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+ ARMword cccr;
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};
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#if 0
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#define MAX_BANK 8
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@@ -212,119 +212,119 @@ struct ARMul_Energy
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typedef struct mem_bank
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{
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- ARMword (*read_byte) (ARMul_State * state, ARMword addr);
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- void (*write_byte) (ARMul_State * state, ARMword addr, ARMword data);
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- ARMword (*read_halfword) (ARMul_State * state, ARMword addr);
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- void (*write_halfword) (ARMul_State * state, ARMword addr,
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- ARMword data);
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- ARMword (*read_word) (ARMul_State * state, ARMword addr);
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- void (*write_word) (ARMul_State * state, ARMword addr, ARMword data);
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- unsigned int addr, len;
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- char filename[MAX_STR];
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- unsigned type; //chy 2003-09-21: maybe io,ram,rom
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+ ARMword (*read_byte) (ARMul_State * state, ARMword addr);
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+ void (*write_byte) (ARMul_State * state, ARMword addr, ARMword data);
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+ ARMword (*read_halfword) (ARMul_State * state, ARMword addr);
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+ void (*write_halfword) (ARMul_State * state, ARMword addr,
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+ ARMword data);
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+ ARMword (*read_word) (ARMul_State * state, ARMword addr);
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+ void (*write_word) (ARMul_State * state, ARMword addr, ARMword data);
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+ unsigned int addr, len;
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+ char filename[MAX_STR];
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+ unsigned type; //chy 2003-09-21: maybe io,ram,rom
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} mem_bank_t;
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typedef struct
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{
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- int bank_num;
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- int current_num; /*current num of bank */
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- mem_bank_t mem_banks[MAX_BANK];
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+ int bank_num;
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+ int current_num; /*current num of bank */
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+ mem_bank_t mem_banks[MAX_BANK];
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} mem_config_t;
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#endif
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#define VFP_REG_NUM 64
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struct ARMul_State
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{
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- ARMword Emulate; /* to start and stop emulation */
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- unsigned EndCondition; /* reason for stopping */
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- unsigned ErrorCode; /* type of illegal instruction */
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-
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- /* Order of the following register should not be modified */
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- ARMword Reg[16]; /* the current register file */
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- ARMword Cpsr; /* the current psr */
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- ARMword Spsr_copy;
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- ARMword phys_pc;
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- ARMword Reg_usr[2];
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- ARMword Reg_svc[2]; /* R13_SVC R14_SVC */
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- ARMword Reg_abort[2]; /* R13_ABORT R14_ABORT */
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- ARMword Reg_undef[2]; /* R13 UNDEF R14 UNDEF */
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- ARMword Reg_irq[2]; /* R13_IRQ R14_IRQ */
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- ARMword Reg_firq[7]; /* R8---R14 FIRQ */
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- ARMword Spsr[7]; /* the exception psr's */
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- ARMword Mode; /* the current mode */
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- ARMword Bank; /* the current register bank */
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- ARMword exclusive_tag;
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- ARMword exclusive_state;
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- ARMword exclusive_result;
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- ARMword CP15[VFP_BASE - CP15_BASE];
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- ARMword VFP[3]; /* FPSID, FPSCR, and FPEXC */
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- /* VFPv2 and VFPv3-D16 has 16 doubleword registers (D0-D16 or S0-S31).
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- VFPv3-D32/ASIMD may have up to 32 doubleword registers (D0-D31),
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- and only 32 singleword registers are accessible (S0-S31). */
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- ARMword ExtReg[VFP_REG_NUM];
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- /* ---- End of the ordered registers ---- */
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-
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- ARMword RegBank[7][16]; /* all the registers */
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- //chy:2003-08-19, used in arm xscale
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- /* 40 bit accumulator. We always keep this 64 bits wide,
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- and move only 40 bits out of it in an MRA insn. */
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- ARMdword Accumulator;
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-
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- ARMword NFlag, ZFlag, CFlag, VFlag, IFFlags; /* dummy flags for speed */
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+ ARMword Emulate; /* to start and stop emulation */
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+ unsigned EndCondition; /* reason for stopping */
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+ unsigned ErrorCode; /* type of illegal instruction */
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+
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+ /* Order of the following register should not be modified */
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+ ARMword Reg[16]; /* the current register file */
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+ ARMword Cpsr; /* the current psr */
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+ ARMword Spsr_copy;
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+ ARMword phys_pc;
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+ ARMword Reg_usr[2];
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+ ARMword Reg_svc[2]; /* R13_SVC R14_SVC */
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+ ARMword Reg_abort[2]; /* R13_ABORT R14_ABORT */
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+ ARMword Reg_undef[2]; /* R13 UNDEF R14 UNDEF */
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+ ARMword Reg_irq[2]; /* R13_IRQ R14_IRQ */
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+ ARMword Reg_firq[7]; /* R8---R14 FIRQ */
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+ ARMword Spsr[7]; /* the exception psr's */
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+ ARMword Mode; /* the current mode */
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+ ARMword Bank; /* the current register bank */
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+ ARMword exclusive_tag;
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+ ARMword exclusive_state;
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+ ARMword exclusive_result;
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+ ARMword CP15[VFP_BASE - CP15_BASE];
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+ ARMword VFP[3]; /* FPSID, FPSCR, and FPEXC */
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+ /* VFPv2 and VFPv3-D16 has 16 doubleword registers (D0-D16 or S0-S31).
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+ VFPv3-D32/ASIMD may have up to 32 doubleword registers (D0-D31),
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+ and only 32 singleword registers are accessible (S0-S31). */
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+ ARMword ExtReg[VFP_REG_NUM];
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+ /* ---- End of the ordered registers ---- */
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+
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+ ARMword RegBank[7][16]; /* all the registers */
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+ //chy:2003-08-19, used in arm xscale
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+ /* 40 bit accumulator. We always keep this 64 bits wide,
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+ and move only 40 bits out of it in an MRA insn. */
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+ ARMdword Accumulator;
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+
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+ ARMword NFlag, ZFlag, CFlag, VFlag, IFFlags; /* dummy flags for speed */
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unsigned long long int icounter, debug_icounter, kernel_icounter;
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unsigned int shifter_carry_out;
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//ARMword translate_pc;
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- /* add armv6 flags dyf:2010-08-09 */
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- ARMword GEFlag, EFlag, AFlag, QFlags;
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- //chy:2003-08-19, used in arm v5e|xscale
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- ARMword SFlag;
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+ /* add armv6 flags dyf:2010-08-09 */
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+ ARMword GEFlag, EFlag, AFlag, QFlags;
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+ //chy:2003-08-19, used in arm v5e|xscale
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+ ARMword SFlag;
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#ifdef MODET
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- ARMword TFlag; /* Thumb state */
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+ ARMword TFlag; /* Thumb state */
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#endif
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- ARMword instr, pc, temp; /* saved register state */
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- ARMword loaded, decoded; /* saved pipeline state */
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- //chy 2006-04-12 for ICE breakpoint
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- ARMword loaded_addr, decoded_addr; /* saved pipeline state addr*/
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- unsigned int NumScycles, NumNcycles, NumIcycles, NumCcycles, NumFcycles; /* emulated cycles used */
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- unsigned long long NumInstrs; /* the number of instructions executed */
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- unsigned NextInstr;
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- unsigned VectorCatch; /* caught exception mask */
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- unsigned CallDebug; /* set to call the debugger */
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- unsigned CanWatch; /* set by memory interface if its willing to suffer the
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- overhead of checking for watchpoints on each memory
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- access */
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- unsigned int StopHandle;
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-
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- char *CommandLine; /* Command Line from ARMsd */
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-
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- ARMul_CPInits *CPInit[16]; /* coprocessor initialisers */
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- ARMul_CPExits *CPExit[16]; /* coprocessor finalisers */
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- ARMul_LDCs *LDC[16]; /* LDC instruction */
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- ARMul_STCs *STC[16]; /* STC instruction */
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- ARMul_MRCs *MRC[16]; /* MRC instruction */
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- ARMul_MCRs *MCR[16]; /* MCR instruction */
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- ARMul_MRRCs *MRRC[16]; /* MRRC instruction */
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- ARMul_MCRRs *MCRR[16]; /* MCRR instruction */
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- ARMul_CDPs *CDP[16]; /* CDP instruction */
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- ARMul_CPReads *CPRead[16]; /* Read CP register */
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- ARMul_CPWrites *CPWrite[16]; /* Write CP register */
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- unsigned char *CPData[16]; /* Coprocessor data */
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- unsigned char const *CPRegWords[16]; /* map of coprocessor register sizes */
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-
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- unsigned EventSet; /* the number of events in the queue */
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- unsigned int Now; /* time to the nearest cycle */
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- struct EventNode **EventPtr; /* the event list */
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-
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- unsigned Debug; /* show instructions as they are executed */
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- unsigned NresetSig; /* reset the processor */
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- unsigned NfiqSig;
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- unsigned NirqSig;
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-
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- unsigned abortSig;
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- unsigned NtransSig;
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- unsigned bigendSig;
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- unsigned prog32Sig;
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- unsigned data32Sig;
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- unsigned syscallSig;
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+ ARMword instr, pc, temp; /* saved register state */
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+ ARMword loaded, decoded; /* saved pipeline state */
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+ //chy 2006-04-12 for ICE breakpoint
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+ ARMword loaded_addr, decoded_addr; /* saved pipeline state addr*/
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+ unsigned int NumScycles, NumNcycles, NumIcycles, NumCcycles, NumFcycles; /* emulated cycles used */
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+ unsigned long long NumInstrs; /* the number of instructions executed */
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+ unsigned NextInstr;
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+ unsigned VectorCatch; /* caught exception mask */
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+ unsigned CallDebug; /* set to call the debugger */
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+ unsigned CanWatch; /* set by memory interface if its willing to suffer the
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+ overhead of checking for watchpoints on each memory
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+ access */
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+ unsigned int StopHandle;
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+
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+ char *CommandLine; /* Command Line from ARMsd */
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+
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+ ARMul_CPInits *CPInit[16]; /* coprocessor initialisers */
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+ ARMul_CPExits *CPExit[16]; /* coprocessor finalisers */
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+ ARMul_LDCs *LDC[16]; /* LDC instruction */
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+ ARMul_STCs *STC[16]; /* STC instruction */
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+ ARMul_MRCs *MRC[16]; /* MRC instruction */
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+ ARMul_MCRs *MCR[16]; /* MCR instruction */
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+ ARMul_MRRCs *MRRC[16]; /* MRRC instruction */
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+ ARMul_MCRRs *MCRR[16]; /* MCRR instruction */
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+ ARMul_CDPs *CDP[16]; /* CDP instruction */
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+ ARMul_CPReads *CPRead[16]; /* Read CP register */
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+ ARMul_CPWrites *CPWrite[16]; /* Write CP register */
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+ unsigned char *CPData[16]; /* Coprocessor data */
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+ unsigned char const *CPRegWords[16]; /* map of coprocessor register sizes */
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+
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+ unsigned EventSet; /* the number of events in the queue */
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+ unsigned int Now; /* time to the nearest cycle */
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+ struct EventNode **EventPtr; /* the event list */
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+
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+ unsigned Debug; /* show instructions as they are executed */
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+ unsigned NresetSig; /* reset the processor */
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+ unsigned NfiqSig;
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+ unsigned NirqSig;
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+
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+ unsigned abortSig;
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+ unsigned NtransSig;
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+ unsigned bigendSig;
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+ unsigned prog32Sig;
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+ unsigned data32Sig;
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+ unsigned syscallSig;
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/* 2004-05-09 chy
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|
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----------------------------------------------------------
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@@ -357,115 +357,115 @@ on later processors, this bit reads as 1 and ignores writes.
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So, if lateabtSig=1, then it means Late Abort Model(Base Updated Abort Model)
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if lateabtSig=0, then it means Base Restored Abort Model
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*/
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- unsigned lateabtSig;
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-
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|
- ARMword Vector; /* synthesize aborts in cycle modes */
|
|
|
- ARMword Aborted; /* sticky flag for aborts */
|
|
|
- ARMword Reseted; /* sticky flag for Reset */
|
|
|
- ARMword Inted, LastInted; /* sticky flags for interrupts */
|
|
|
- ARMword Base; /* extra hand for base writeback */
|
|
|
- ARMword AbortAddr; /* to keep track of Prefetch aborts */
|
|
|
-
|
|
|
- const struct Dbg_HostosInterface *hostif;
|
|
|
-
|
|
|
- int verbose; /* non-zero means print various messages like the banner */
|
|
|
-
|
|
|
- mmu_state_t mmu;
|
|
|
- int mmu_inited;
|
|
|
- //mem_state_t mem;
|
|
|
- /*remove io_state to skyeye_mach_*.c files */
|
|
|
- //io_state_t io;
|
|
|
- /* point to a interrupt pending register. now for skyeye-ne2k.c
|
|
|
- * later should move somewhere. e.g machine_config_t*/
|
|
|
-
|
|
|
-
|
|
|
- //chy: 2003-08-11, for different arm core type
|
|
|
- unsigned is_v4; /* Are we emulating a v4 architecture (or higher) ? */
|
|
|
- unsigned is_v5; /* Are we emulating a v5 architecture ? */
|
|
|
- unsigned is_v5e; /* Are we emulating a v5e architecture ? */
|
|
|
- unsigned is_v6; /* Are we emulating a v6 architecture ? */
|
|
|
- unsigned is_v7; /* Are we emulating a v7 architecture ? */
|
|
|
- unsigned is_XScale; /* Are we emulating an XScale architecture ? */
|
|
|
- unsigned is_iWMMXt; /* Are we emulating an iWMMXt co-processor ? */
|
|
|
- unsigned is_ep9312; /* Are we emulating a Cirrus Maverick co-processor ? */
|
|
|
- //chy 2005-09-19
|
|
|
- unsigned is_pxa27x; /* Are we emulating a Intel PXA27x co-processor ? */
|
|
|
- //chy: seems only used in xscale's CP14
|
|
|
- unsigned int LastTime; /* Value of last call to ARMul_Time() */
|
|
|
- ARMword CP14R0_CCD; /* used to count 64 clock cycles with CP14 R0 bit 3 set */
|
|
|
+ unsigned lateabtSig;
|
|
|
+
|
|
|
+ ARMword Vector; /* synthesize aborts in cycle modes */
|
|
|
+ ARMword Aborted; /* sticky flag for aborts */
|
|
|
+ ARMword Reseted; /* sticky flag for Reset */
|
|
|
+ ARMword Inted, LastInted; /* sticky flags for interrupts */
|
|
|
+ ARMword Base; /* extra hand for base writeback */
|
|
|
+ ARMword AbortAddr; /* to keep track of Prefetch aborts */
|
|
|
+
|
|
|
+ const struct Dbg_HostosInterface *hostif;
|
|
|
+
|
|
|
+ int verbose; /* non-zero means print various messages like the banner */
|
|
|
+
|
|
|
+ mmu_state_t mmu;
|
|
|
+ int mmu_inited;
|
|
|
+ //mem_state_t mem;
|
|
|
+ /*remove io_state to skyeye_mach_*.c files */
|
|
|
+ //io_state_t io;
|
|
|
+ /* point to a interrupt pending register. now for skyeye-ne2k.c
|
|
|
+ * later should move somewhere. e.g machine_config_t*/
|
|
|
+
|
|
|
+
|
|
|
+ //chy: 2003-08-11, for different arm core type
|
|
|
+ unsigned is_v4; /* Are we emulating a v4 architecture (or higher) ? */
|
|
|
+ unsigned is_v5; /* Are we emulating a v5 architecture ? */
|
|
|
+ unsigned is_v5e; /* Are we emulating a v5e architecture ? */
|
|
|
+ unsigned is_v6; /* Are we emulating a v6 architecture ? */
|
|
|
+ unsigned is_v7; /* Are we emulating a v7 architecture ? */
|
|
|
+ unsigned is_XScale; /* Are we emulating an XScale architecture ? */
|
|
|
+ unsigned is_iWMMXt; /* Are we emulating an iWMMXt co-processor ? */
|
|
|
+ unsigned is_ep9312; /* Are we emulating a Cirrus Maverick co-processor ? */
|
|
|
+ //chy 2005-09-19
|
|
|
+ unsigned is_pxa27x; /* Are we emulating a Intel PXA27x co-processor ? */
|
|
|
+ //chy: seems only used in xscale's CP14
|
|
|
+ unsigned int LastTime; /* Value of last call to ARMul_Time() */
|
|
|
+ ARMword CP14R0_CCD; /* used to count 64 clock cycles with CP14 R0 bit 3 set */
|
|
|
|
|
|
|
|
|
//added by ksh:for handle different machs io 2004-3-5
|
|
|
- ARMul_io mach_io;
|
|
|
+ ARMul_io mach_io;
|
|
|
|
|
|
/*added by ksh,2004-11-26,some energy profiling*/
|
|
|
- ARMul_Energy energy;
|
|
|
+ ARMul_Energy energy;
|
|
|
|
|
|
//teawater add for next_dis 2004.10.27-----------------------
|
|
|
- int disassemble;
|
|
|
+ int disassemble;
|
|
|
//AJ2D------------------------------------------
|
|
|
|
|
|
//teawater add for arm2x86 2005.02.15-------------------------------------------
|
|
|
- u32 trap;
|
|
|
- u32 tea_break_addr;
|
|
|
- u32 tea_break_ok;
|
|
|
- int tea_pc;
|
|
|
+ u32 trap;
|
|
|
+ u32 tea_break_addr;
|
|
|
+ u32 tea_break_ok;
|
|
|
+ int tea_pc;
|
|
|
//AJ2D--------------------------------------------------------------------------
|
|
|
//teawater add for arm2x86 2005.07.03-------------------------------------------
|
|
|
|
|
|
- /*
|
|
|
- * 2007-01-24 removed the term-io functions by Anthony Lee,
|
|
|
- * moved to "device/uart/skyeye_uart_stdio.c".
|
|
|
- */
|
|
|
+ /*
|
|
|
+ * 2007-01-24 removed the term-io functions by Anthony Lee,
|
|
|
+ * moved to "device/uart/skyeye_uart_stdio.c".
|
|
|
+ */
|
|
|
|
|
|
//AJ2D--------------------------------------------------------------------------
|
|
|
//teawater add for arm2x86 2005.07.05-------------------------------------------
|
|
|
- //arm_arm A2-18
|
|
|
- int abort_model; //0 Base Restored Abort Model, 1 the Early Abort Model, 2 Base Updated Abort Model
|
|
|
+ //arm_arm A2-18
|
|
|
+ int abort_model; //0 Base Restored Abort Model, 1 the Early Abort Model, 2 Base Updated Abort Model
|
|
|
//AJ2D--------------------------------------------------------------------------
|
|
|
//teawater change for return if running tb dirty 2005.07.09---------------------
|
|
|
- void *tb_now;
|
|
|
+ void *tb_now;
|
|
|
//AJ2D--------------------------------------------------------------------------
|
|
|
|
|
|
//teawater add for record reg value to ./reg.txt 2005.07.10---------------------
|
|
|
- FILE *tea_reg_fd;
|
|
|
+ FILE *tea_reg_fd;
|
|
|
//AJ2D--------------------------------------------------------------------------
|
|
|
|
|
|
/*added by ksh in 2005-10-1*/
|
|
|
- cpu_config_t *cpu;
|
|
|
- //mem_config_t *mem_bank;
|
|
|
+ cpu_config_t *cpu;
|
|
|
+ //mem_config_t *mem_bank;
|
|
|
|
|
|
/* added LPC remap function */
|
|
|
- int vector_remap_flag;
|
|
|
- u32 vector_remap_addr;
|
|
|
- u32 vector_remap_size;
|
|
|
-
|
|
|
- u32 step;
|
|
|
- u32 cycle;
|
|
|
- int stop_simulator;
|
|
|
- conf_object_t *dyncom_cpu;
|
|
|
+ int vector_remap_flag;
|
|
|
+ u32 vector_remap_addr;
|
|
|
+ u32 vector_remap_size;
|
|
|
+
|
|
|
+ u32 step;
|
|
|
+ u32 cycle;
|
|
|
+ int stop_simulator;
|
|
|
+ conf_object_t *dyncom_cpu;
|
|
|
//teawater add DBCT_TEST_SPEED 2005.10.04---------------------------------------
|
|
|
#ifdef DBCT_TEST_SPEED
|
|
|
- uint64_t instr_count;
|
|
|
-#endif //DBCT_TEST_SPEED
|
|
|
-// FILE * state_log;
|
|
|
+ uint64_t instr_count;
|
|
|
+#endif //DBCT_TEST_SPEED
|
|
|
+// FILE * state_log;
|
|
|
//diff log
|
|
|
//#if DIFF_STATE
|
|
|
- FILE * state_log;
|
|
|
+ FILE * state_log;
|
|
|
//#endif
|
|
|
- /* monitored memory for exclusice access */
|
|
|
- ARMword exclusive_tag_array[128];
|
|
|
- /* 1 means exclusive access and 0 means open access */
|
|
|
- ARMword exclusive_access_state;
|
|
|
-
|
|
|
- memory_space_intf space;
|
|
|
- u32 CurrInstr;
|
|
|
- u32 last_pc; /* the last pc executed */
|
|
|
- u32 last_instr; /* the last inst executed */
|
|
|
- u32 WriteAddr[17];
|
|
|
- u32 WriteData[17];
|
|
|
- u32 WritePc[17];
|
|
|
- u32 CurrWrite;
|
|
|
+ /* monitored memory for exclusice access */
|
|
|
+ ARMword exclusive_tag_array[128];
|
|
|
+ /* 1 means exclusive access and 0 means open access */
|
|
|
+ ARMword exclusive_access_state;
|
|
|
+
|
|
|
+ memory_space_intf space;
|
|
|
+ u32 CurrInstr;
|
|
|
+ u32 last_pc; /* the last pc executed */
|
|
|
+ u32 last_instr; /* the last inst executed */
|
|
|
+ u32 WriteAddr[17];
|
|
|
+ u32 WriteData[17];
|
|
|
+ u32 WritePc[17];
|
|
|
+ u32 CurrWrite;
|
|
|
};
|
|
|
#define DIFF_WRITE 0
|
|
|
|
|
|
@@ -510,7 +510,7 @@ typedef ARMul_State arm_core_t;
|
|
|
#define ARM61 ARM2
|
|
|
#define ARM3 ARM2
|
|
|
|
|
|
-#ifdef ARM60 /* previous definition in armopts.h */
|
|
|
+#ifdef ARM60 /* previous definition in armopts.h */
|
|
|
#undef ARM60
|
|
|
#endif
|
|
|
|
|
|
@@ -526,9 +526,9 @@ typedef ARMul_State arm_core_t;
|
|
|
* Macros to extract instruction fields *
|
|
|
\***************************************************************************/
|
|
|
|
|
|
-#define BIT(n) ( (ARMword)(instr>>(n))&1) /* bit n of instruction */
|
|
|
-#define BITS(m,n) ( (ARMword)(instr<<(31-(n))) >> ((31-(n))+(m)) ) /* bits m to n of instr */
|
|
|
-#define TOPBITS(n) (instr >> (n)) /* bits 31 to n of instr */
|
|
|
+#define BIT(n) ( (ARMword)(instr>>(n))&1) /* bit n of instruction */
|
|
|
+#define BITS(m,n) ( (ARMword)(instr<<(31-(n))) >> ((31-(n))+(m)) ) /* bits m to n of instr */
|
|
|
+#define TOPBITS(n) (instr >> (n)) /* bits 31 to n of instr */
|
|
|
|
|
|
/***************************************************************************\
|
|
|
* The hardware vector addresses *
|
|
|
@@ -542,7 +542,7 @@ typedef ARMul_State arm_core_t;
|
|
|
#define ARMAddrExceptnV 20L
|
|
|
#define ARMIRQV 24L
|
|
|
#define ARMFIQV 28L
|
|
|
-#define ARMErrorV 32L /* This is an offset, not an address ! */
|
|
|
+#define ARMErrorV 32L /* This is an offset, not an address ! */
|
|
|
|
|
|
#define ARMul_ResetV ARMResetV
|
|
|
#define ARMul_UndefinedInstrV ARMUndefinedInstrV
|
|
|
@@ -598,7 +598,7 @@ extern "C" {
|
|
|
extern void ARMul_EmulateInit (void);
|
|
|
extern void ARMul_Reset (ARMul_State * state);
|
|
|
#ifdef __cplusplus
|
|
|
- }
|
|
|
+ }
|
|
|
#endif
|
|
|
extern ARMul_State *ARMul_NewState (ARMul_State * state);
|
|
|
extern ARMword ARMul_DoProg (ARMul_State * state);
|
|
|
@@ -608,7 +608,7 @@ extern ARMword ARMul_DoInstr (ARMul_State * state);
|
|
|
\***************************************************************************/
|
|
|
|
|
|
extern void ARMul_ScheduleEvent (ARMul_State * state, unsigned int delay,
|
|
|
- unsigned (*func) ());
|
|
|
+ unsigned (*func) ());
|
|
|
extern void ARMul_EnvokeEvent (ARMul_State * state);
|
|
|
extern unsigned int ARMul_Time (ARMul_State * state);
|
|
|
|
|
|
@@ -617,9 +617,9 @@ extern unsigned int ARMul_Time (ARMul_State * state);
|
|
|
\***************************************************************************/
|
|
|
|
|
|
extern ARMword ARMul_GetReg (ARMul_State * state, unsigned mode,
|
|
|
- unsigned reg);
|
|
|
+ unsigned reg);
|
|
|
extern void ARMul_SetReg (ARMul_State * state, unsigned mode, unsigned reg,
|
|
|
- ARMword value);
|
|
|
+ ARMword value);
|
|
|
extern ARMword ARMul_GetPC (ARMul_State * state);
|
|
|
extern ARMword ARMul_GetNextPC (ARMul_State * state);
|
|
|
extern void ARMul_SetPC (ARMul_State * state, ARMword value);
|
|
|
@@ -637,11 +637,11 @@ extern void ARMul_SetSPSR (ARMul_State * state, ARMword mode, ARMword value);
|
|
|
|
|
|
extern void ARMul_Abort (ARMul_State * state, ARMword address);
|
|
|
#ifdef MODET
|
|
|
-#define ARMul_ABORTWORD (state->TFlag ? 0xefffdfff : 0xefffffff) /* SWI -1 */
|
|
|
+#define ARMul_ABORTWORD (state->TFlag ? 0xefffdfff : 0xefffffff) /* SWI -1 */
|
|
|
#define ARMul_PREFETCHABORT(address) if (state->AbortAddr == 1) \
|
|
|
state->AbortAddr = (address & (state->TFlag ? ~1L : ~3L))
|
|
|
#else
|
|
|
-#define ARMul_ABORTWORD 0xefffffff /* SWI -1 */
|
|
|
+#define ARMul_ABORTWORD 0xefffffff /* SWI -1 */
|
|
|
#define ARMul_PREFETCHABORT(address) if (state->AbortAddr == 1) \
|
|
|
state->AbortAddr = (address & ~3L)
|
|
|
#endif
|
|
|
@@ -654,20 +654,20 @@ extern void ARMul_Abort (ARMul_State * state, ARMword address);
|
|
|
\***************************************************************************/
|
|
|
|
|
|
extern unsigned ARMul_MemoryInit (ARMul_State * state,
|
|
|
- unsigned int initmemsize);
|
|
|
+ unsigned int initmemsize);
|
|
|
extern void ARMul_MemoryExit (ARMul_State * state);
|
|
|
|
|
|
extern ARMword ARMul_LoadInstrS (ARMul_State * state, ARMword address,
|
|
|
- ARMword isize);
|
|
|
+ ARMword isize);
|
|
|
extern ARMword ARMul_LoadInstrN (ARMul_State * state, ARMword address,
|
|
|
- ARMword isize);
|
|
|
+ ARMword isize);
|
|
|
#ifdef __cplusplus
|
|
|
extern "C" {
|
|
|
#endif
|
|
|
extern ARMword ARMul_ReLoadInstr (ARMul_State * state, ARMword address,
|
|
|
- ARMword isize);
|
|
|
+ ARMword isize);
|
|
|
#ifdef __cplusplus
|
|
|
- }
|
|
|
+ }
|
|
|
#endif
|
|
|
extern ARMword ARMul_LoadWordS (ARMul_State * state, ARMword address);
|
|
|
extern ARMword ARMul_LoadWordN (ARMul_State * state, ARMword address);
|
|
|
@@ -675,34 +675,34 @@ extern ARMword ARMul_LoadHalfWord (ARMul_State * state, ARMword address);
|
|
|
extern ARMword ARMul_LoadByte (ARMul_State * state, ARMword address);
|
|
|
|
|
|
extern void ARMul_StoreWordS (ARMul_State * state, ARMword address,
|
|
|
- ARMword data);
|
|
|
+ ARMword data);
|
|
|
extern void ARMul_StoreWordN (ARMul_State * state, ARMword address,
|
|
|
- ARMword data);
|
|
|
+ ARMword data);
|
|
|
extern void ARMul_StoreHalfWord (ARMul_State * state, ARMword address,
|
|
|
- ARMword data);
|
|
|
+ ARMword data);
|
|
|
extern void ARMul_StoreByte (ARMul_State * state, ARMword address,
|
|
|
- ARMword data);
|
|
|
+ ARMword data);
|
|
|
|
|
|
extern ARMword ARMul_SwapWord (ARMul_State * state, ARMword address,
|
|
|
- ARMword data);
|
|
|
+ ARMword data);
|
|
|
extern ARMword ARMul_SwapByte (ARMul_State * state, ARMword address,
|
|
|
- ARMword data);
|
|
|
+ ARMword data);
|
|
|
|
|
|
extern void ARMul_Icycles (ARMul_State * state, unsigned number,
|
|
|
- ARMword address);
|
|
|
+ ARMword address);
|
|
|
extern void ARMul_Ccycles (ARMul_State * state, unsigned number,
|
|
|
- ARMword address);
|
|
|
+ ARMword address);
|
|
|
|
|
|
extern ARMword ARMul_ReadWord (ARMul_State * state, ARMword address);
|
|
|
extern ARMword ARMul_ReadByte (ARMul_State * state, ARMword address);
|
|
|
extern void ARMul_WriteWord (ARMul_State * state, ARMword address,
|
|
|
- ARMword data);
|
|
|
+ ARMword data);
|
|
|
extern void ARMul_WriteByte (ARMul_State * state, ARMword address,
|
|
|
- ARMword data);
|
|
|
+ ARMword data);
|
|
|
|
|
|
extern ARMword ARMul_MemAccess (ARMul_State * state, ARMword, ARMword,
|
|
|
- ARMword, ARMword, ARMword, ARMword, ARMword,
|
|
|
- ARMword, ARMword, ARMword);
|
|
|
+ ARMword, ARMword, ARMword, ARMword, ARMword,
|
|
|
+ ARMword, ARMword, ARMword);
|
|
|
|
|
|
/***************************************************************************\
|
|
|
* Definitons of things in the co-processor interface *
|
|
|
@@ -746,12 +746,12 @@ extern ARMword ARMul_MemAccess (ARMul_State * state, ARMword, ARMword,
|
|
|
extern unsigned ARMul_CoProInit (ARMul_State * state);
|
|
|
extern void ARMul_CoProExit (ARMul_State * state);
|
|
|
extern void ARMul_CoProAttach (ARMul_State * state, unsigned number,
|
|
|
- ARMul_CPInits * init, ARMul_CPExits * exit,
|
|
|
- ARMul_LDCs * ldc, ARMul_STCs * stc,
|
|
|
- ARMul_MRCs * mrc, ARMul_MCRs * mcr,
|
|
|
- ARMul_MRRCs * mrrc, ARMul_MCRRs * mcrr,
|
|
|
- ARMul_CDPs * cdp,
|
|
|
- ARMul_CPReads * read, ARMul_CPWrites * write);
|
|
|
+ ARMul_CPInits * init, ARMul_CPExits * exit,
|
|
|
+ ARMul_LDCs * ldc, ARMul_STCs * stc,
|
|
|
+ ARMul_MRCs * mrc, ARMul_MCRs * mcr,
|
|
|
+ ARMul_MRRCs * mrrc, ARMul_MCRRs * mcrr,
|
|
|
+ ARMul_CDPs * cdp,
|
|
|
+ ARMul_CPReads * read, ARMul_CPWrites * write);
|
|
|
extern void ARMul_CoProDetach (ARMul_State * state, unsigned number);
|
|
|
|
|
|
/***************************************************************************\
|
|
|
@@ -775,7 +775,7 @@ extern ARMword ARMul_OSLastErrorP (ARMul_State * state);
|
|
|
|
|
|
extern ARMword ARMul_Debug (ARMul_State * state, ARMword pc, ARMword instr);
|
|
|
extern unsigned ARMul_OSException (ARMul_State * state, ARMword vector,
|
|
|
- ARMword pc);
|
|
|
+ ARMword pc);
|
|
|
extern int rdi_log;
|
|
|
|
|
|
/***************************************************************************\
|
|
|
@@ -783,9 +783,9 @@ extern int rdi_log;
|
|
|
\***************************************************************************/
|
|
|
|
|
|
#ifdef macintosh
|
|
|
-pascal void SpinCursor (short increment); /* copied from CursorCtl.h */
|
|
|
+pascal void SpinCursor (short increment); /* copied from CursorCtl.h */
|
|
|
# define HOURGLASS SpinCursor( 1 )
|
|
|
-# define HOURGLASS_RATE 1023 /* 2^n - 1 */
|
|
|
+# define HOURGLASS_RATE 1023 /* 2^n - 1 */
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#endif
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//teawater add for arm2x86 2005.02.14-------------------------------------------
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@@ -821,38 +821,38 @@ pascal void SpinCursor (short increment); /* copied from CursorCtl.h */
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#define NV 15
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#ifndef NFLAG
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-#define NFLAG state->NFlag
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+#define NFLAG state->NFlag
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#endif //NFLAG
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#ifndef ZFLAG
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-#define ZFLAG state->ZFlag
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+#define ZFLAG state->ZFlag
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#endif //ZFLAG
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#ifndef CFLAG
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-#define CFLAG state->CFlag
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+#define CFLAG state->CFlag
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#endif //CFLAG
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#ifndef VFLAG
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-#define VFLAG state->VFlag
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+#define VFLAG state->VFlag
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#endif //VFLAG
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#ifndef IFLAG
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-#define IFLAG (state->IFFlags >> 1)
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+#define IFLAG (state->IFFlags >> 1)
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#endif //IFLAG
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#ifndef FFLAG
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-#define FFLAG (state->IFFlags & 1)
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+#define FFLAG (state->IFFlags & 1)
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#endif //FFLAG
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#ifndef IFFLAGS
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-#define IFFLAGS state->IFFlags
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+#define IFFLAGS state->IFFlags
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#endif //VFLAG
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-#define FLAG_MASK 0xf0000000
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-#define NBIT_SHIFT 31
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-#define ZBIT_SHIFT 30
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-#define CBIT_SHIFT 29
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-#define VBIT_SHIFT 28
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+#define FLAG_MASK 0xf0000000
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+#define NBIT_SHIFT 31
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+#define ZBIT_SHIFT 30
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+#define CBIT_SHIFT 29
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+#define VBIT_SHIFT 28
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#ifdef DBCT
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//teawater change for local tb branch directly jump 2005.10.18------------------
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#include "dbct/list.h"
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@@ -875,10 +875,10 @@ pascal void SpinCursor (short increment); /* copied from CursorCtl.h */
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state->Reg[4],state->Reg[5],state->Reg[6],state->Reg[7], \
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state->Reg[8],state->Reg[9],state->Reg[10],state->Reg[11], \
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state->Reg[12],state->Reg[13],state->Reg[14],state->Reg[15], \
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- state->Cpsr, state->Spsr[0], state->Spsr[1], state->Spsr[2],\
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+ state->Cpsr, state->Spsr[0], state->Spsr[1], state->Spsr[2],\
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state->Spsr[3],state->Spsr[4], state->Spsr[5], state->Spsr[6],\
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- state->Mode,state->Bank,state->ErrorCode,state->instr,state->pc,\
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- state->temp,state->loaded,state->decoded);}
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+ state->Mode,state->Bank,state->ErrorCode,state->instr,state->pc,\
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+ state->temp,state->loaded,state->decoded);}
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#define SKYEYE_OUTMOREREGS(fd) { fprintf ((fd),"\
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RUs %x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,\
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@@ -911,13 +911,13 @@ RUn %x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x\n",\
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state->RegBank[5][4],state->RegBank[5][5],state->RegBank[5][6],state->RegBank[5][7], \
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state->RegBank[5][8],state->RegBank[5][9],state->RegBank[5][10],state->RegBank[5][11], \
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state->RegBank[5][12],state->RegBank[5][13],state->RegBank[5][14],state->RegBank[5][15] \
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- );}
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+ );}
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#define SA1110 0x6901b110
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#define SA1100 0x4401a100
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-#define PXA250 0x69052100
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-#define PXA270 0x69054110
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+#define PXA250 0x69052100
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+#define PXA270 0x69054110
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//#define PXA250 0x69052903
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// 0x69052903; //PXA250 B1 from intel 278522-001.pdf
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bunnei