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@@ -1,25 +1,12 @@
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// SPDX-FileCopyrightText: Copyright 2018 yuzu Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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-#include <cinttypes>
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-#include <memory>
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-#include <dynarmic/interface/A64/a64.h>
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-#include <dynarmic/interface/A64/config.h>
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-#include "common/assert.h"
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-#include "common/literals.h"
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-#include "common/logging/log.h"
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-#include "common/page_table.h"
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#include "common/settings.h"
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#include "core/arm/dynarmic/arm_dynarmic.h"
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#include "core/arm/dynarmic/arm_dynarmic_64.h"
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#include "core/arm/dynarmic/dynarmic_exclusive_monitor.h"
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-#include "core/core.h"
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#include "core/core_timing.h"
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-#include "core/debugger/debugger.h"
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-#include "core/hardware_properties.h"
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#include "core/hle/kernel/k_process.h"
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-#include "core/hle/kernel/svc.h"
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-#include "core/memory.h"
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namespace Core {
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@@ -28,92 +15,92 @@ using namespace Common::Literals;
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class DynarmicCallbacks64 : public Dynarmic::A64::UserCallbacks {
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public:
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- explicit DynarmicCallbacks64(ARM_Dynarmic_64& parent_)
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- : parent{parent_}, memory(parent.system.ApplicationMemory()),
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- debugger_enabled{parent.system.DebuggerEnabled()},
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- check_memory_access{debugger_enabled ||
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- !Settings::values.cpuopt_ignore_memory_aborts.GetValue()} {}
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+ explicit DynarmicCallbacks64(ArmDynarmic64& parent, const Kernel::KProcess* process)
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+ : m_parent{parent}, m_memory(process->GetMemory()),
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+ m_process(process), m_debugger_enabled{parent.m_system.DebuggerEnabled()},
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+ m_check_memory_access{m_debugger_enabled ||
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+ !Settings::values.cpuopt_ignore_memory_aborts.GetValue()} {}
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u8 MemoryRead8(u64 vaddr) override {
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CheckMemoryAccess(vaddr, 1, Kernel::DebugWatchpointType::Read);
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- return memory.Read8(vaddr);
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+ return m_memory.Read8(vaddr);
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}
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u16 MemoryRead16(u64 vaddr) override {
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CheckMemoryAccess(vaddr, 2, Kernel::DebugWatchpointType::Read);
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- return memory.Read16(vaddr);
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+ return m_memory.Read16(vaddr);
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}
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u32 MemoryRead32(u64 vaddr) override {
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CheckMemoryAccess(vaddr, 4, Kernel::DebugWatchpointType::Read);
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- return memory.Read32(vaddr);
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+ return m_memory.Read32(vaddr);
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}
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u64 MemoryRead64(u64 vaddr) override {
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CheckMemoryAccess(vaddr, 8, Kernel::DebugWatchpointType::Read);
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- return memory.Read64(vaddr);
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+ return m_memory.Read64(vaddr);
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}
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Vector MemoryRead128(u64 vaddr) override {
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CheckMemoryAccess(vaddr, 16, Kernel::DebugWatchpointType::Read);
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- return {memory.Read64(vaddr), memory.Read64(vaddr + 8)};
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+ return {m_memory.Read64(vaddr), m_memory.Read64(vaddr + 8)};
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}
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std::optional<u32> MemoryReadCode(u64 vaddr) override {
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- if (!memory.IsValidVirtualAddressRange(vaddr, sizeof(u32))) {
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+ if (!m_memory.IsValidVirtualAddressRange(vaddr, sizeof(u32))) {
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return std::nullopt;
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}
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- return memory.Read32(vaddr);
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+ return m_memory.Read32(vaddr);
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}
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void MemoryWrite8(u64 vaddr, u8 value) override {
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if (CheckMemoryAccess(vaddr, 1, Kernel::DebugWatchpointType::Write)) {
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- memory.Write8(vaddr, value);
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+ m_memory.Write8(vaddr, value);
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}
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}
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void MemoryWrite16(u64 vaddr, u16 value) override {
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if (CheckMemoryAccess(vaddr, 2, Kernel::DebugWatchpointType::Write)) {
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- memory.Write16(vaddr, value);
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+ m_memory.Write16(vaddr, value);
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}
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}
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void MemoryWrite32(u64 vaddr, u32 value) override {
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if (CheckMemoryAccess(vaddr, 4, Kernel::DebugWatchpointType::Write)) {
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- memory.Write32(vaddr, value);
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+ m_memory.Write32(vaddr, value);
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}
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}
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void MemoryWrite64(u64 vaddr, u64 value) override {
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if (CheckMemoryAccess(vaddr, 8, Kernel::DebugWatchpointType::Write)) {
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- memory.Write64(vaddr, value);
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+ m_memory.Write64(vaddr, value);
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}
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}
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void MemoryWrite128(u64 vaddr, Vector value) override {
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if (CheckMemoryAccess(vaddr, 16, Kernel::DebugWatchpointType::Write)) {
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- memory.Write64(vaddr, value[0]);
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- memory.Write64(vaddr + 8, value[1]);
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+ m_memory.Write64(vaddr, value[0]);
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+ m_memory.Write64(vaddr + 8, value[1]);
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}
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}
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bool MemoryWriteExclusive8(u64 vaddr, std::uint8_t value, std::uint8_t expected) override {
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return CheckMemoryAccess(vaddr, 1, Kernel::DebugWatchpointType::Write) &&
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- memory.WriteExclusive8(vaddr, value, expected);
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+ m_memory.WriteExclusive8(vaddr, value, expected);
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}
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bool MemoryWriteExclusive16(u64 vaddr, std::uint16_t value, std::uint16_t expected) override {
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return CheckMemoryAccess(vaddr, 2, Kernel::DebugWatchpointType::Write) &&
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- memory.WriteExclusive16(vaddr, value, expected);
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+ m_memory.WriteExclusive16(vaddr, value, expected);
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}
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bool MemoryWriteExclusive32(u64 vaddr, std::uint32_t value, std::uint32_t expected) override {
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return CheckMemoryAccess(vaddr, 4, Kernel::DebugWatchpointType::Write) &&
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- memory.WriteExclusive32(vaddr, value, expected);
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+ m_memory.WriteExclusive32(vaddr, value, expected);
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}
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bool MemoryWriteExclusive64(u64 vaddr, std::uint64_t value, std::uint64_t expected) override {
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return CheckMemoryAccess(vaddr, 8, Kernel::DebugWatchpointType::Write) &&
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- memory.WriteExclusive64(vaddr, value, expected);
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+ m_memory.WriteExclusive64(vaddr, value, expected);
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}
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bool MemoryWriteExclusive128(u64 vaddr, Vector value, Vector expected) override {
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return CheckMemoryAccess(vaddr, 16, Kernel::DebugWatchpointType::Write) &&
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- memory.WriteExclusive128(vaddr, value, expected);
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+ m_memory.WriteExclusive128(vaddr, value, expected);
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}
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void InterpreterFallback(u64 pc, std::size_t num_instructions) override {
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- parent.LogBacktrace();
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+ m_parent.LogBacktrace(m_process);
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LOG_ERROR(Core_ARM,
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"Unimplemented instruction @ 0x{:X} for {} instructions (instr = {:08X})", pc,
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- num_instructions, memory.Read32(pc));
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+ num_instructions, m_memory.Read32(pc));
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ReturnException(pc, PrefetchAbort);
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}
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@@ -124,11 +111,11 @@ public:
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static constexpr u64 ICACHE_LINE_SIZE = 64;
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const u64 cache_line_start = value & ~(ICACHE_LINE_SIZE - 1);
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- parent.system.InvalidateCpuInstructionCacheRange(cache_line_start, ICACHE_LINE_SIZE);
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+ m_parent.InvalidateCacheRange(cache_line_start, ICACHE_LINE_SIZE);
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break;
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}
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case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoU:
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- parent.system.InvalidateCpuInstructionCaches();
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+ m_parent.ClearInstructionCache();
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break;
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case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoUInnerSharable:
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default:
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@@ -136,7 +123,7 @@ public:
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break;
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}
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- parent.jit.load()->HaltExecution(Dynarmic::HaltReason::CacheInvalidation);
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+ m_parent.m_jit->HaltExecution(Dynarmic::HaltReason::CacheInvalidation);
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}
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void ExceptionRaised(u64 pc, Dynarmic::A64::Exception exception) override {
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@@ -152,26 +139,24 @@ public:
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ReturnException(pc, PrefetchAbort);
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return;
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default:
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- if (debugger_enabled) {
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+ if (m_debugger_enabled) {
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ReturnException(pc, InstructionBreakpoint);
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return;
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}
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- parent.LogBacktrace();
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+ m_parent.LogBacktrace(m_process);
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LOG_CRITICAL(Core_ARM, "ExceptionRaised(exception = {}, pc = {:08X}, code = {:08X})",
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- static_cast<std::size_t>(exception), pc, memory.Read32(pc));
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+ static_cast<std::size_t>(exception), pc, m_memory.Read32(pc));
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}
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}
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- void CallSVC(u32 swi) override {
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- parent.svc_swi = swi;
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- parent.jit.load()->HaltExecution(SupervisorCall);
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+ void CallSVC(u32 svc) override {
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+ m_parent.m_svc = svc;
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+ m_parent.m_jit->HaltExecution(SupervisorCall);
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}
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void AddTicks(u64 ticks) override {
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- if (parent.uses_wall_clock) {
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- return;
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- }
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+ ASSERT_MSG(!m_parent.m_uses_wall_clock, "Dynarmic ticking disabled");
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// Divide the number of ticks by the amount of CPU cores. TODO(Subv): This yields only a
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// rough approximation of the amount of executed ticks in the system, it may be thrown off
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@@ -182,44 +167,39 @@ public:
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// Always execute at least one tick.
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amortized_ticks = std::max<u64>(amortized_ticks, 1);
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- parent.system.CoreTiming().AddTicks(amortized_ticks);
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+ m_parent.m_system.CoreTiming().AddTicks(amortized_ticks);
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}
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u64 GetTicksRemaining() override {
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- if (parent.uses_wall_clock) {
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- if (!IsInterrupted()) {
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- return minimum_run_cycles;
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- }
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- return 0U;
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- }
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+ ASSERT_MSG(!m_parent.m_uses_wall_clock, "Dynarmic ticking disabled");
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- return std::max<s64>(parent.system.CoreTiming().GetDowncount(), 0);
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+ return std::max<s64>(m_parent.m_system.CoreTiming().GetDowncount(), 0);
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}
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u64 GetCNTPCT() override {
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- return parent.system.CoreTiming().GetClockTicks();
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+ return m_parent.m_system.CoreTiming().GetClockTicks();
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}
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bool CheckMemoryAccess(u64 addr, u64 size, Kernel::DebugWatchpointType type) {
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- if (!check_memory_access) {
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+ if (!m_check_memory_access) {
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return true;
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}
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- if (!memory.IsValidVirtualAddressRange(addr, size)) {
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+ if (!m_memory.IsValidVirtualAddressRange(addr, size)) {
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LOG_CRITICAL(Core_ARM, "Stopping execution due to unmapped memory access at {:#x}",
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addr);
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- parent.jit.load()->HaltExecution(PrefetchAbort);
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+ m_parent.m_jit->HaltExecution(PrefetchAbort);
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return false;
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}
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- if (!debugger_enabled) {
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+ if (!m_debugger_enabled) {
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return true;
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}
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- const auto match{parent.MatchingWatchpoint(addr, size, type)};
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+ const auto match{m_parent.MatchingWatchpoint(addr, size, type)};
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if (match) {
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- parent.halted_watchpoint = match;
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- parent.jit.load()->HaltExecution(DataAbort);
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+ m_parent.m_halted_watchpoint = match;
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+ m_parent.m_jit->HaltExecution(DataAbort);
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return false;
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}
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@@ -227,30 +207,27 @@ public:
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}
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void ReturnException(u64 pc, Dynarmic::HaltReason hr) {
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- parent.SaveContext(parent.breakpoint_context);
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- parent.breakpoint_context.pc = pc;
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- parent.jit.load()->HaltExecution(hr);
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+ m_parent.GetContext(m_parent.m_breakpoint_context);
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+ m_parent.m_breakpoint_context.pc = pc;
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+ m_parent.m_jit->HaltExecution(hr);
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}
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- bool IsInterrupted() {
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- return parent.system.Kernel().PhysicalCore(parent.core_index).IsInterrupted();
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- }
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-
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- ARM_Dynarmic_64& parent;
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- Core::Memory::Memory& memory;
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- u64 tpidrro_el0 = 0;
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- u64 tpidr_el0 = 0;
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- const bool debugger_enabled{};
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- const bool check_memory_access{};
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- static constexpr u64 minimum_run_cycles = 10000U;
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+ ArmDynarmic64& m_parent;
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+ Core::Memory::Memory& m_memory;
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+ u64 m_tpidrro_el0{};
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+ u64 m_tpidr_el0{};
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+ const Kernel::KProcess* m_process{};
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+ const bool m_debugger_enabled{};
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+ const bool m_check_memory_access{};
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+ static constexpr u64 MinimumRunCycles = 10000U;
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};
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-std::shared_ptr<Dynarmic::A64::Jit> ARM_Dynarmic_64::MakeJit(Common::PageTable* page_table,
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- std::size_t address_space_bits) const {
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+std::shared_ptr<Dynarmic::A64::Jit> ArmDynarmic64::MakeJit(Common::PageTable* page_table,
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+ std::size_t address_space_bits) const {
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Dynarmic::A64::UserConfig config;
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// Callbacks
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- config.callbacks = cb.get();
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+ config.callbacks = m_cb.get();
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// Memory
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if (page_table) {
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@@ -271,12 +248,12 @@ std::shared_ptr<Dynarmic::A64::Jit> ARM_Dynarmic_64::MakeJit(Common::PageTable*
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}
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// Multi-process state
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- config.processor_id = core_index;
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- config.global_monitor = &exclusive_monitor.monitor;
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+ config.processor_id = m_core_index;
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+ config.global_monitor = &m_exclusive_monitor.monitor;
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// System registers
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- config.tpidrro_el0 = &cb->tpidrro_el0;
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- config.tpidr_el0 = &cb->tpidr_el0;
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+ config.tpidrro_el0 = &m_cb->m_tpidrro_el0;
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+ config.tpidr_el0 = &m_cb->m_tpidr_el0;
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config.dczid_el0 = 4;
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config.ctr_el0 = 0x8444c004;
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config.cntfrq_el0 = Hardware::CNTFREQ;
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@@ -285,8 +262,8 @@ std::shared_ptr<Dynarmic::A64::Jit> ARM_Dynarmic_64::MakeJit(Common::PageTable*
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config.define_unpredictable_behaviour = true;
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// Timing
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- config.wall_clock_cntpct = uses_wall_clock;
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- config.enable_cycle_counting = true;
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+ config.wall_clock_cntpct = m_uses_wall_clock;
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+ config.enable_cycle_counting = !m_uses_wall_clock;
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// Code cache size
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#ifdef ARCHITECTURE_arm64
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@@ -296,7 +273,7 @@ std::shared_ptr<Dynarmic::A64::Jit> ARM_Dynarmic_64::MakeJit(Common::PageTable*
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#endif
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// Allow memory fault handling to work
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- if (system.DebuggerEnabled()) {
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+ if (m_system.DebuggerEnabled()) {
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config.check_halt_on_memory_access = true;
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}
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@@ -384,147 +361,112 @@ std::shared_ptr<Dynarmic::A64::Jit> ARM_Dynarmic_64::MakeJit(Common::PageTable*
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return std::make_shared<Dynarmic::A64::Jit>(config);
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}
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-HaltReason ARM_Dynarmic_64::RunJit() {
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- return TranslateHaltReason(jit.load()->Run());
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-}
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-
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-HaltReason ARM_Dynarmic_64::StepJit() {
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- return TranslateHaltReason(jit.load()->Step());
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-}
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-
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-u32 ARM_Dynarmic_64::GetSvcNumber() const {
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- return svc_swi;
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-}
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-
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-const Kernel::DebugWatchpoint* ARM_Dynarmic_64::HaltedWatchpoint() const {
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- return halted_watchpoint;
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-}
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-
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-void ARM_Dynarmic_64::RewindBreakpointInstruction() {
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- LoadContext(breakpoint_context);
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-}
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-
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-ARM_Dynarmic_64::ARM_Dynarmic_64(System& system_, bool uses_wall_clock_,
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- DynarmicExclusiveMonitor& exclusive_monitor_,
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- std::size_t core_index_)
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- : ARM_Interface{system_, uses_wall_clock_},
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- cb(std::make_unique<DynarmicCallbacks64>(*this)), core_index{core_index_},
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- exclusive_monitor{exclusive_monitor_}, null_jit{MakeJit(nullptr, 48)}, jit{null_jit.get()} {}
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-
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-ARM_Dynarmic_64::~ARM_Dynarmic_64() = default;
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-
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-void ARM_Dynarmic_64::SetPC(u64 pc) {
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- jit.load()->SetPC(pc);
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-}
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-
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-u64 ARM_Dynarmic_64::GetPC() const {
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- return jit.load()->GetPC();
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+HaltReason ArmDynarmic64::RunThread(Kernel::KThread* thread) {
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+ m_jit->ClearExclusiveState();
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+ return TranslateHaltReason(m_jit->Run());
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}
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-u64 ARM_Dynarmic_64::GetSP() const {
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- return jit.load()->GetSP();
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+HaltReason ArmDynarmic64::StepThread(Kernel::KThread* thread) {
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+ m_jit->ClearExclusiveState();
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+ return TranslateHaltReason(m_jit->Step());
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}
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-u64 ARM_Dynarmic_64::GetReg(int index) const {
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- return jit.load()->GetRegister(index);
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+u32 ArmDynarmic64::GetSvcNumber() const {
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+ return m_svc;
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}
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-void ARM_Dynarmic_64::SetReg(int index, u64 value) {
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- jit.load()->SetRegister(index, value);
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-}
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+void ArmDynarmic64::GetSvcArguments(std::span<uint64_t, 8> args) const {
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+ Dynarmic::A64::Jit& j = *m_jit;
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-u128 ARM_Dynarmic_64::GetVectorReg(int index) const {
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- return jit.load()->GetVector(index);
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+ for (size_t i = 0; i < 8; i++) {
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+ args[i] = j.GetRegister(i);
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+ }
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}
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-void ARM_Dynarmic_64::SetVectorReg(int index, u128 value) {
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- jit.load()->SetVector(index, value);
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-}
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+void ArmDynarmic64::SetSvcArguments(std::span<const uint64_t, 8> args) {
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+ Dynarmic::A64::Jit& j = *m_jit;
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-u32 ARM_Dynarmic_64::GetPSTATE() const {
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- return jit.load()->GetPstate();
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+ for (size_t i = 0; i < 8; i++) {
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+ j.SetRegister(i, args[i]);
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+ }
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}
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-void ARM_Dynarmic_64::SetPSTATE(u32 pstate) {
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- jit.load()->SetPstate(pstate);
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+const Kernel::DebugWatchpoint* ArmDynarmic64::HaltedWatchpoint() const {
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+ return m_halted_watchpoint;
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}
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-u64 ARM_Dynarmic_64::GetTlsAddress() const {
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- return cb->tpidrro_el0;
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+void ArmDynarmic64::RewindBreakpointInstruction() {
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+ this->SetContext(m_breakpoint_context);
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}
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-void ARM_Dynarmic_64::SetTlsAddress(u64 address) {
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- cb->tpidrro_el0 = address;
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+ArmDynarmic64::ArmDynarmic64(System& system, bool uses_wall_clock, const Kernel::KProcess* process,
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+ DynarmicExclusiveMonitor& exclusive_monitor, std::size_t core_index)
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|
+ : ArmInterface{uses_wall_clock}, m_system{system}, m_exclusive_monitor{exclusive_monitor},
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+ m_cb(std::make_unique<DynarmicCallbacks64>(*this, process)), m_core_index{core_index} {
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+ auto& page_table = process->GetPageTable().GetBasePageTable();
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|
+ auto& page_table_impl = page_table.GetImpl();
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|
+ m_jit = MakeJit(&page_table_impl, page_table.GetAddressSpaceWidth());
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|
}
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-u64 ARM_Dynarmic_64::GetTPIDR_EL0() const {
|
|
|
- return cb->tpidr_el0;
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|
|
-}
|
|
|
+ArmDynarmic64::~ArmDynarmic64() = default;
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|
|
|
|
-void ARM_Dynarmic_64::SetTPIDR_EL0(u64 value) {
|
|
|
- cb->tpidr_el0 = value;
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|
+void ArmDynarmic64::SetTpidrroEl0(u64 value) {
|
|
|
+ m_cb->m_tpidrro_el0 = value;
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|
|
}
|
|
|
|
|
|
-void ARM_Dynarmic_64::SaveContext(ThreadContext64& ctx) const {
|
|
|
- Dynarmic::A64::Jit* j = jit.load();
|
|
|
- ctx.cpu_registers = j->GetRegisters();
|
|
|
- ctx.sp = j->GetSP();
|
|
|
- ctx.pc = j->GetPC();
|
|
|
- ctx.pstate = j->GetPstate();
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|
|
- ctx.vector_registers = j->GetVectors();
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|
|
- ctx.fpcr = j->GetFpcr();
|
|
|
- ctx.fpsr = j->GetFpsr();
|
|
|
- ctx.tpidr = cb->tpidr_el0;
|
|
|
-}
|
|
|
+void ArmDynarmic64::GetContext(Kernel::Svc::ThreadContext& ctx) const {
|
|
|
+ Dynarmic::A64::Jit& j = *m_jit;
|
|
|
+ auto gpr = j.GetRegisters();
|
|
|
+ auto fpr = j.GetVectors();
|
|
|
|
|
|
-void ARM_Dynarmic_64::LoadContext(const ThreadContext64& ctx) {
|
|
|
- Dynarmic::A64::Jit* j = jit.load();
|
|
|
- j->SetRegisters(ctx.cpu_registers);
|
|
|
- j->SetSP(ctx.sp);
|
|
|
- j->SetPC(ctx.pc);
|
|
|
- j->SetPstate(ctx.pstate);
|
|
|
- j->SetVectors(ctx.vector_registers);
|
|
|
- j->SetFpcr(ctx.fpcr);
|
|
|
- j->SetFpsr(ctx.fpsr);
|
|
|
- SetTPIDR_EL0(ctx.tpidr);
|
|
|
+ // TODO: this is inconvenient
|
|
|
+ for (size_t i = 0; i < 29; i++) {
|
|
|
+ ctx.r[i] = gpr[i];
|
|
|
+ }
|
|
|
+ ctx.fp = gpr[29];
|
|
|
+ ctx.lr = gpr[30];
|
|
|
+
|
|
|
+ ctx.sp = j.GetSP();
|
|
|
+ ctx.pc = j.GetPC();
|
|
|
+ ctx.pstate = j.GetPstate();
|
|
|
+ ctx.v = fpr;
|
|
|
+ ctx.fpcr = j.GetFpcr();
|
|
|
+ ctx.fpsr = j.GetFpsr();
|
|
|
+ ctx.tpidr = m_cb->m_tpidr_el0;
|
|
|
}
|
|
|
|
|
|
-void ARM_Dynarmic_64::SignalInterrupt() {
|
|
|
- jit.load()->HaltExecution(BreakLoop);
|
|
|
-}
|
|
|
+void ArmDynarmic64::SetContext(const Kernel::Svc::ThreadContext& ctx) {
|
|
|
+ Dynarmic::A64::Jit& j = *m_jit;
|
|
|
|
|
|
-void ARM_Dynarmic_64::ClearInterrupt() {
|
|
|
- jit.load()->ClearHalt(BreakLoop);
|
|
|
-}
|
|
|
+ // TODO: this is inconvenient
|
|
|
+ std::array<u64, 31> gpr;
|
|
|
|
|
|
-void ARM_Dynarmic_64::ClearInstructionCache() {
|
|
|
- jit.load()->ClearCache();
|
|
|
+ for (size_t i = 0; i < 29; i++) {
|
|
|
+ gpr[i] = ctx.r[i];
|
|
|
+ }
|
|
|
+ gpr[29] = ctx.fp;
|
|
|
+ gpr[30] = ctx.lr;
|
|
|
+
|
|
|
+ j.SetRegisters(gpr);
|
|
|
+ j.SetSP(ctx.sp);
|
|
|
+ j.SetPC(ctx.pc);
|
|
|
+ j.SetPstate(ctx.pstate);
|
|
|
+ j.SetVectors(ctx.v);
|
|
|
+ j.SetFpcr(ctx.fpcr);
|
|
|
+ j.SetFpsr(ctx.fpsr);
|
|
|
+ m_cb->m_tpidr_el0 = ctx.tpidr;
|
|
|
}
|
|
|
|
|
|
-void ARM_Dynarmic_64::InvalidateCacheRange(u64 addr, std::size_t size) {
|
|
|
- jit.load()->InvalidateCacheRange(addr, size);
|
|
|
+void ArmDynarmic64::SignalInterrupt(Kernel::KThread* thread) {
|
|
|
+ m_jit->HaltExecution(BreakLoop);
|
|
|
}
|
|
|
|
|
|
-void ARM_Dynarmic_64::ClearExclusiveState() {
|
|
|
- jit.load()->ClearExclusiveState();
|
|
|
+void ArmDynarmic64::ClearInstructionCache() {
|
|
|
+ m_jit->ClearCache();
|
|
|
}
|
|
|
|
|
|
-void ARM_Dynarmic_64::PageTableChanged(Common::PageTable& page_table,
|
|
|
- std::size_t new_address_space_size_in_bits) {
|
|
|
- ThreadContext64 ctx{};
|
|
|
- SaveContext(ctx);
|
|
|
-
|
|
|
- auto key = std::make_pair(&page_table, new_address_space_size_in_bits);
|
|
|
- auto iter = jit_cache.find(key);
|
|
|
- if (iter != jit_cache.end()) {
|
|
|
- jit.store(iter->second.get());
|
|
|
- LoadContext(ctx);
|
|
|
- return;
|
|
|
- }
|
|
|
- std::shared_ptr new_jit = MakeJit(&page_table, new_address_space_size_in_bits);
|
|
|
- jit.store(new_jit.get());
|
|
|
- LoadContext(ctx);
|
|
|
- jit_cache.emplace(key, std::move(new_jit));
|
|
|
+void ArmDynarmic64::InvalidateCacheRange(u64 addr, std::size_t size) {
|
|
|
+ m_jit->InvalidateCacheRange(addr, size);
|
|
|
}
|
|
|
|
|
|
} // namespace Core
|