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+// SPDX-FileCopyrightText: Copyright 2023 yuzu Emulator Project
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+// SPDX-License-Identifier: GPL-2.0-or-later
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+
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+#include <thread>
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+
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+#ifdef _MSC_VER
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+#include <intrin.h>
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+#endif
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+
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+#include "common/x64/cpu_detect.h"
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+#include "common/x64/cpu_wait.h"
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+
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+namespace Common::X64 {
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+
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+#ifdef _MSC_VER
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+__forceinline static u64 FencedRDTSC() {
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+ _mm_lfence();
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+ _ReadWriteBarrier();
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+ const u64 result = __rdtsc();
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+ _mm_lfence();
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+ _ReadWriteBarrier();
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+ return result;
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+}
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+
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+__forceinline static void TPAUSE() {
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+ // 100,000 cycles is a reasonable amount of time to wait to save on CPU resources.
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+ // For reference:
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+ // At 1 GHz, 100K cycles is 100us
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+ // At 2 GHz, 100K cycles is 50us
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+ // At 4 GHz, 100K cycles is 25us
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+ static constexpr auto PauseCycles = 100'000;
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+ _tpause(0, FencedRDTSC() + PauseCycles);
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+}
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+#else
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+static u64 FencedRDTSC() {
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+ u64 result;
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+ asm volatile("lfence\n\t"
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+ "rdtsc\n\t"
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+ "shl $32, %%rdx\n\t"
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+ "or %%rdx, %0\n\t"
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+ "lfence"
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+ : "=a"(result)
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+ :
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+ : "rdx", "memory", "cc");
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+ return result;
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+}
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+
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+static void TPAUSE() {
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+ // 100,000 cycles is a reasonable amount of time to wait to save on CPU resources.
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+ // For reference:
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+ // At 1 GHz, 100K cycles is 100us
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+ // At 2 GHz, 100K cycles is 50us
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+ // At 4 GHz, 100K cycles is 25us
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+ static constexpr auto PauseCycles = 100'000;
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+ const auto tsc = FencedRDTSC() + PauseCycles;
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+ const auto eax = static_cast<u32>(tsc & 0xFFFFFFFF);
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+ const auto edx = static_cast<u32>(tsc >> 32);
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+ asm volatile("tpause %0" : : "r"(0), "d"(edx), "a"(eax));
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+}
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+#endif
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+
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+void MicroSleep() {
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+ static const bool has_waitpkg = GetCPUCaps().waitpkg;
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+
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+ if (has_waitpkg) {
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+ TPAUSE();
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+ } else {
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+ std::this_thread::yield();
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+ }
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+}
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+
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+} // namespace Common::X64
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