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@@ -2,417 +2,11 @@
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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-#include "common/bit_field.h"
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-#include "common/microprofile.h"
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-#include "core/core.h"
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-#include "core/hle/ipc.h"
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-#include "core/hle/kernel/event.h"
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-#include "core/hle/kernel/handle_table.h"
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-#include "core/hle/kernel/shared_memory.h"
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-#include "core/hle/result.h"
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#include "core/hle/service/gsp_gpu.h"
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-#include "core/hw/gpu.h"
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-#include "core/hw/hw.h"
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-#include "core/hw/lcd.h"
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-#include "core/memory.h"
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-#include "video_core/debug_utils/debug_utils.h"
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-#include "video_core/gpu_debugger.h"
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-
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-// Main graphics debugger object - TODO: Here is probably not the best place for this
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-GraphicsDebugger g_debugger;
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namespace Service {
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namespace GSP {
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-// Beginning address of HW regs
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-const u32 REGS_BEGIN = 0x1EB00000;
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-
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-namespace ErrCodes {
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-enum {
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- // TODO(purpasmart): Check if this name fits its actual usage
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- OutofRangeOrMisalignedAddress = 513,
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- FirstInitialization = 519,
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-};
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-}
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-
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-constexpr ResultCode RESULT_FIRST_INITIALIZATION(ErrCodes::FirstInitialization, ErrorModule::GX,
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- ErrorSummary::Success, ErrorLevel::Success);
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-constexpr ResultCode ERR_REGS_OUTOFRANGE_OR_MISALIGNED(ErrCodes::OutofRangeOrMisalignedAddress,
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- ErrorModule::GX,
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- ErrorSummary::InvalidArgument,
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- ErrorLevel::Usage); // 0xE0E02A01
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-constexpr ResultCode ERR_REGS_MISALIGNED(ErrorDescription::MisalignedSize, ErrorModule::GX,
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- ErrorSummary::InvalidArgument,
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- ErrorLevel::Usage); // 0xE0E02BF2
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-constexpr ResultCode ERR_REGS_INVALID_SIZE(ErrorDescription::InvalidSize, ErrorModule::GX,
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- ErrorSummary::InvalidArgument,
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- ErrorLevel::Usage); // 0xE0E02BEC
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-
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-/// Event triggered when GSP interrupt has been signalled
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-Kernel::SharedPtr<Kernel::Event> g_interrupt_event;
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-/// GSP shared memoryings
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-Kernel::SharedPtr<Kernel::SharedMemory> g_shared_memory;
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-/// Thread index into interrupt relay queue
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-u32 g_thread_id = 0;
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-
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-static bool gpu_right_acquired = false;
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-static bool first_initialization = true;
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-/// Gets a pointer to a thread command buffer in GSP shared memory
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-static inline u8* GetCommandBuffer(u32 thread_id) {
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- return g_shared_memory->GetPointer(0x800 + (thread_id * sizeof(CommandBuffer)));
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-}
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-
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-FrameBufferUpdate* GetFrameBufferInfo(u32 thread_id, u32 screen_index) {
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- DEBUG_ASSERT_MSG(screen_index < 2, "Invalid screen index");
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-
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- // For each thread there are two FrameBufferUpdate fields
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- u32 offset = 0x200 + (2 * thread_id + screen_index) * sizeof(FrameBufferUpdate);
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- u8* ptr = g_shared_memory->GetPointer(offset);
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- return reinterpret_cast<FrameBufferUpdate*>(ptr);
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-}
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-
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-/// Gets a pointer to the interrupt relay queue for a given thread index
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-static inline InterruptRelayQueue* GetInterruptRelayQueue(u32 thread_id) {
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- u8* ptr = g_shared_memory->GetPointer(sizeof(InterruptRelayQueue) * thread_id);
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- return reinterpret_cast<InterruptRelayQueue*>(ptr);
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-}
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-
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-/**
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- * Writes a single GSP GPU hardware registers with a single u32 value
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- * (For internal use.)
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- *
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- * @param base_address The address of the register in question
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- * @param data Data to be written
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- */
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-static void WriteSingleHWReg(u32 base_address, u32 data) {
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- DEBUG_ASSERT_MSG((base_address & 3) == 0 && base_address < 0x420000,
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- "Write address out of range or misaligned");
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- HW::Write<u32>(base_address + REGS_BEGIN, data);
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-}
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-
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-/**
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- * Writes sequential GSP GPU hardware registers using an array of source data
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- *
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- * @param base_address The address of the first register in the sequence
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- * @param size_in_bytes The number of registers to update (size of data)
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- * @param data_vaddr A pointer to the source data
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- * @return RESULT_SUCCESS if the parameters are valid, error code otherwise
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- */
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-static ResultCode WriteHWRegs(u32 base_address, u32 size_in_bytes, VAddr data_vaddr) {
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- // This magic number is verified to be done by the gsp module
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- const u32 max_size_in_bytes = 0x80;
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-
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- if (base_address & 3 || base_address >= 0x420000) {
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- LOG_ERROR(Service_GSP,
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- "Write address was out of range or misaligned! (address=0x%08x, size=0x%08x)",
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- base_address, size_in_bytes);
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- return ERR_REGS_OUTOFRANGE_OR_MISALIGNED;
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- } else if (size_in_bytes <= max_size_in_bytes) {
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- if (size_in_bytes & 3) {
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- LOG_ERROR(Service_GSP, "Misaligned size 0x%08x", size_in_bytes);
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- return ERR_REGS_MISALIGNED;
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- } else {
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- while (size_in_bytes > 0) {
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- WriteSingleHWReg(base_address, Memory::Read32(data_vaddr));
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-
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- size_in_bytes -= 4;
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- data_vaddr += 4;
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- base_address += 4;
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- }
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- return RESULT_SUCCESS;
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- }
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-
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- } else {
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- LOG_ERROR(Service_GSP, "Out of range size 0x%08x", size_in_bytes);
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- return ERR_REGS_INVALID_SIZE;
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- }
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-}
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-
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-/**
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- * Updates sequential GSP GPU hardware registers using parallel arrays of source data and masks.
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- * For each register, the value is updated only where the mask is high
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- *
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- * @param base_address The address of the first register in the sequence
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- * @param size_in_bytes The number of registers to update (size of data)
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- * @param data_vaddr A virtual address to the source data to use for updates
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- * @param masks_vaddr A virtual address to the masks
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- * @return RESULT_SUCCESS if the parameters are valid, error code otherwise
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- */
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-static ResultCode WriteHWRegsWithMask(u32 base_address, u32 size_in_bytes, VAddr data_vaddr,
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- VAddr masks_vaddr) {
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- // This magic number is verified to be done by the gsp module
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- const u32 max_size_in_bytes = 0x80;
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-
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- if (base_address & 3 || base_address >= 0x420000) {
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- LOG_ERROR(Service_GSP,
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- "Write address was out of range or misaligned! (address=0x%08x, size=0x%08x)",
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- base_address, size_in_bytes);
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- return ERR_REGS_OUTOFRANGE_OR_MISALIGNED;
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- } else if (size_in_bytes <= max_size_in_bytes) {
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- if (size_in_bytes & 3) {
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- LOG_ERROR(Service_GSP, "Misaligned size 0x%08x", size_in_bytes);
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- return ERR_REGS_MISALIGNED;
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- } else {
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- while (size_in_bytes > 0) {
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- const u32 reg_address = base_address + REGS_BEGIN;
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-
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- u32 reg_value;
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- HW::Read<u32>(reg_value, reg_address);
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-
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- u32 data = Memory::Read32(data_vaddr);
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- u32 mask = Memory::Read32(masks_vaddr);
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-
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- // Update the current value of the register only for set mask bits
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- reg_value = (reg_value & ~mask) | (data & mask);
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-
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- WriteSingleHWReg(base_address, reg_value);
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-
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- size_in_bytes -= 4;
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- data_vaddr += 4;
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- masks_vaddr += 4;
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- base_address += 4;
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- }
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- return RESULT_SUCCESS;
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- }
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-
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- } else {
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- LOG_ERROR(Service_GSP, "Out of range size 0x%08x", size_in_bytes);
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- return ERR_REGS_INVALID_SIZE;
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- }
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-}
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-
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-/**
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- * GSP_GPU::WriteHWRegs service function
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- *
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- * Writes sequential GSP GPU hardware registers
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- *
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- * Inputs:
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- * 1 : address of first GPU register
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- * 2 : number of registers to write sequentially
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- * 4 : pointer to source data array
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- */
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-static void WriteHWRegs(Interface* self) {
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- u32* cmd_buff = Kernel::GetCommandBuffer();
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- u32 reg_addr = cmd_buff[1];
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- u32 size = cmd_buff[2];
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- VAddr src = cmd_buff[4];
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-
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- cmd_buff[1] = WriteHWRegs(reg_addr, size, src).raw;
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-}
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-
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-/**
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- * GSP_GPU::WriteHWRegsWithMask service function
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- *
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- * Updates sequential GSP GPU hardware registers using masks
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- *
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- * Inputs:
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- * 1 : address of first GPU register
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- * 2 : number of registers to update sequentially
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- * 4 : pointer to source data array
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- * 6 : pointer to mask array
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- */
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-static void WriteHWRegsWithMask(Interface* self) {
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- u32* cmd_buff = Kernel::GetCommandBuffer();
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- u32 reg_addr = cmd_buff[1];
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- u32 size = cmd_buff[2];
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-
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- VAddr src_data = cmd_buff[4];
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- VAddr mask_data = cmd_buff[6];
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-
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- cmd_buff[1] = WriteHWRegsWithMask(reg_addr, size, src_data, mask_data).raw;
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-}
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-
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-/// Read a GSP GPU hardware register
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-static void ReadHWRegs(Interface* self) {
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- u32* cmd_buff = Kernel::GetCommandBuffer();
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- u32 reg_addr = cmd_buff[1];
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- u32 size = cmd_buff[2];
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-
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- // TODO: Return proper error codes
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- if (reg_addr + size >= 0x420000) {
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- LOG_ERROR(Service_GSP, "Read address out of range! (address=0x%08x, size=0x%08x)", reg_addr,
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- size);
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- return;
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- }
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-
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- // size should be word-aligned
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- if ((size % 4) != 0) {
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- LOG_ERROR(Service_GSP, "Invalid size 0x%08x", size);
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- return;
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- }
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-
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- VAddr dst_vaddr = cmd_buff[0x41];
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-
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- while (size > 0) {
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- u32 value;
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- HW::Read<u32>(value, reg_addr + REGS_BEGIN);
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-
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- Memory::Write32(dst_vaddr, value);
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-
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- size -= 4;
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- dst_vaddr += 4;
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- reg_addr += 4;
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- }
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-}
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-
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-ResultCode SetBufferSwap(u32 screen_id, const FrameBufferInfo& info) {
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- u32 base_address = 0x400000;
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- PAddr phys_address_left = Memory::VirtualToPhysicalAddress(info.address_left);
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- PAddr phys_address_right = Memory::VirtualToPhysicalAddress(info.address_right);
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- if (info.active_fb == 0) {
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- WriteSingleHWReg(
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- base_address +
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- 4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].address_left1)),
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- phys_address_left);
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- WriteSingleHWReg(
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- base_address +
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- 4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].address_right1)),
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- phys_address_right);
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- } else {
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- WriteSingleHWReg(
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- base_address +
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- 4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].address_left2)),
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- phys_address_left);
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- WriteSingleHWReg(
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- base_address +
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- 4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].address_right2)),
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- phys_address_right);
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- }
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- WriteSingleHWReg(base_address +
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- 4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].stride)),
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- info.stride);
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- WriteSingleHWReg(
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- base_address +
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- 4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].color_format)),
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- info.format);
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- WriteSingleHWReg(
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- base_address + 4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].active_fb)),
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- info.shown_fb);
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-
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- if (Pica::g_debug_context)
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- Pica::g_debug_context->OnEvent(Pica::DebugContext::Event::BufferSwapped, nullptr);
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-
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- if (screen_id == 0) {
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- MicroProfileFlip();
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- Core::System::GetInstance().perf_stats.EndGameFrame();
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- }
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-
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- return RESULT_SUCCESS;
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-}
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-
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-/**
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- * GSP_GPU::SetBufferSwap service function
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- *
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- * Updates GPU display framebuffer configuration using the specified parameters.
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- *
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- * Inputs:
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- * 1 : Screen ID (0 = top screen, 1 = bottom screen)
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- * 2-7 : FrameBufferInfo structure
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- * Outputs:
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- * 1: Result code
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- */
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-static void SetBufferSwap(Interface* self) {
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- u32* cmd_buff = Kernel::GetCommandBuffer();
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- u32 screen_id = cmd_buff[1];
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- FrameBufferInfo* fb_info = (FrameBufferInfo*)&cmd_buff[2];
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-
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- cmd_buff[1] = SetBufferSwap(screen_id, *fb_info).raw;
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-}
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-
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-/**
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- * GSP_GPU::FlushDataCache service function
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- *
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- * This Function is a no-op, We aren't emulating the CPU cache any time soon.
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- *
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- * Inputs:
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- * 1 : Address
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- * 2 : Size
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- * 3 : Value 0, some descriptor for the KProcess Handle
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- * 4 : KProcess handle
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- * Outputs:
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- * 1 : Result of function, 0 on success, otherwise error code
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- */
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-static void FlushDataCache(Interface* self) {
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- u32* cmd_buff = Kernel::GetCommandBuffer();
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- u32 address = cmd_buff[1];
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- u32 size = cmd_buff[2];
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- u32 process = cmd_buff[4];
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-
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- // TODO(purpasmart96): Verify return header on HW
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-
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- cmd_buff[1] = RESULT_SUCCESS.raw; // No error
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-
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- LOG_DEBUG(Service_GSP, "(STUBBED) called address=0x%08X, size=0x%08X, process=0x%08X", address,
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- size, process);
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-}
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-
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-/**
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- * GSP_GPU::SetAxiConfigQoSMode service function
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- * Inputs:
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- * 1 : Mode, unused in emulator
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- * Outputs:
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- * 1 : Result of function, 0 on success, otherwise error code
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- */
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-static void SetAxiConfigQoSMode(Interface* self) {
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- u32* cmd_buff = Kernel::GetCommandBuffer();
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- u32 mode = cmd_buff[1];
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-
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- cmd_buff[1] = RESULT_SUCCESS.raw; // No error
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-
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- LOG_DEBUG(Service_GSP, "(STUBBED) called mode=0x%08X", mode);
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-}
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-
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-/**
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- * GSP_GPU::RegisterInterruptRelayQueue service function
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- * Inputs:
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- * 1 : "Flags" field, purpose is unknown
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- * 3 : Handle to GSP synchronization event
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- * Outputs:
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- * 1 : Result of function, 0x2A07 on success, otherwise error code
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- * 2 : Thread index into GSP command buffer
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- * 4 : Handle to GSP shared memory
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- */
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-static void RegisterInterruptRelayQueue(Interface* self) {
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- u32* cmd_buff = Kernel::GetCommandBuffer();
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- u32 flags = cmd_buff[1];
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-
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- g_interrupt_event = Kernel::g_handle_table.Get<Kernel::Event>(cmd_buff[3]);
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- // TODO(mailwl): return right error code instead assert
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- ASSERT_MSG((g_interrupt_event != nullptr), "handle is not valid!");
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-
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- g_interrupt_event->name = "GSP_GPU::interrupt_event";
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-
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- if (first_initialization) {
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|
- // This specific code is required for a successful initialization, rather than 0
|
|
|
- first_initialization = false;
|
|
|
- cmd_buff[1] = RESULT_FIRST_INITIALIZATION.raw;
|
|
|
- } else {
|
|
|
- cmd_buff[1] = RESULT_SUCCESS.raw;
|
|
|
- }
|
|
|
- cmd_buff[2] = g_thread_id++; // Thread ID
|
|
|
- cmd_buff[4] = Kernel::g_handle_table.Create(g_shared_memory).Unwrap(); // GSP shared memory
|
|
|
-
|
|
|
- g_interrupt_event->Signal(); // TODO(bunnei): Is this correct?
|
|
|
-
|
|
|
- LOG_WARNING(Service_GSP, "called, flags=0x%08X", flags);
|
|
|
-}
|
|
|
-
|
|
|
-/**
|
|
|
- * GSP_GPU::UnregisterInterruptRelayQueue service function
|
|
|
- * Outputs:
|
|
|
- * 1 : Result of function, 0 on success, otherwise error code
|
|
|
- */
|
|
|
-static void UnregisterInterruptRelayQueue(Interface* self) {
|
|
|
- u32* cmd_buff = Kernel::GetCommandBuffer();
|
|
|
-
|
|
|
- g_thread_id = 0;
|
|
|
- g_interrupt_event = nullptr;
|
|
|
-
|
|
|
- cmd_buff[1] = RESULT_SUCCESS.raw;
|
|
|
-
|
|
|
- LOG_WARNING(Service_GSP, "(STUBBED) called");
|
|
|
-}
|
|
|
-
|
|
|
/**
|
|
|
* Signals that the specified interrupt type has occurred to userland code
|
|
|
* @param interrupt_id ID of interrupt that is being signalled
|
|
|
@@ -420,383 +14,13 @@ static void UnregisterInterruptRelayQueue(Interface* self) {
|
|
|
* @todo This probably does not belong in the GSP module, instead move to video_core
|
|
|
*/
|
|
|
void SignalInterrupt(InterruptId interrupt_id) {
|
|
|
- if (!gpu_right_acquired) {
|
|
|
- return;
|
|
|
- }
|
|
|
- if (nullptr == g_interrupt_event) {
|
|
|
- LOG_WARNING(Service_GSP, "cannot synchronize until GSP event has been created!");
|
|
|
- return;
|
|
|
- }
|
|
|
- if (nullptr == g_shared_memory) {
|
|
|
- LOG_WARNING(Service_GSP, "cannot synchronize until GSP shared memory has been created!");
|
|
|
- return;
|
|
|
- }
|
|
|
- for (int thread_id = 0; thread_id < 0x4; ++thread_id) {
|
|
|
- InterruptRelayQueue* interrupt_relay_queue = GetInterruptRelayQueue(thread_id);
|
|
|
- u8 next = interrupt_relay_queue->index;
|
|
|
- next += interrupt_relay_queue->number_interrupts;
|
|
|
- next = next % 0x34; // 0x34 is the number of interrupt slots
|
|
|
-
|
|
|
- interrupt_relay_queue->number_interrupts += 1;
|
|
|
-
|
|
|
- interrupt_relay_queue->slot[next] = interrupt_id;
|
|
|
- interrupt_relay_queue->error_code = 0x0; // No error
|
|
|
-
|
|
|
- // Update framebuffer information if requested
|
|
|
- // TODO(yuriks): Confirm where this code should be called. It is definitely updated without
|
|
|
- // executing any GSP commands, only waiting on the event.
|
|
|
- int screen_id =
|
|
|
- (interrupt_id == InterruptId::PDC0) ? 0 : (interrupt_id == InterruptId::PDC1) ? 1 : -1;
|
|
|
- if (screen_id != -1) {
|
|
|
- FrameBufferUpdate* info = GetFrameBufferInfo(thread_id, screen_id);
|
|
|
- if (info->is_dirty) {
|
|
|
- SetBufferSwap(screen_id, info->framebuffer_info[info->index]);
|
|
|
- info->is_dirty.Assign(false);
|
|
|
- }
|
|
|
- }
|
|
|
- }
|
|
|
- g_interrupt_event->Signal();
|
|
|
-}
|
|
|
-
|
|
|
-MICROPROFILE_DEFINE(GPU_GSP_DMA, "GPU", "GSP DMA", MP_RGB(100, 0, 255));
|
|
|
-
|
|
|
-/// Executes the next GSP command
|
|
|
-static void ExecuteCommand(const Command& command, u32 thread_id) {
|
|
|
- // Utility function to convert register ID to address
|
|
|
- static auto WriteGPURegister = [](u32 id, u32 data) {
|
|
|
- GPU::Write<u32>(0x1EF00000 + 4 * id, data);
|
|
|
- };
|
|
|
-
|
|
|
- switch (command.id) {
|
|
|
-
|
|
|
- // GX request DMA - typically used for copying memory from GSP heap to VRAM
|
|
|
- case CommandId::REQUEST_DMA: {
|
|
|
- MICROPROFILE_SCOPE(GPU_GSP_DMA);
|
|
|
-
|
|
|
- // TODO: Consider attempting rasterizer-accelerated surface blit if that usage is ever
|
|
|
- // possible/likely
|
|
|
- Memory::RasterizerFlushVirtualRegion(command.dma_request.source_address,
|
|
|
- command.dma_request.size, Memory::FlushMode::Flush);
|
|
|
- Memory::RasterizerFlushVirtualRegion(command.dma_request.dest_address,
|
|
|
- command.dma_request.size,
|
|
|
- Memory::FlushMode::FlushAndInvalidate);
|
|
|
-
|
|
|
- // TODO(Subv): These memory accesses should not go through the application's memory mapping.
|
|
|
- // They should go through the GSP module's memory mapping.
|
|
|
- Memory::CopyBlock(command.dma_request.dest_address, command.dma_request.source_address,
|
|
|
- command.dma_request.size);
|
|
|
- SignalInterrupt(InterruptId::DMA);
|
|
|
- break;
|
|
|
- }
|
|
|
- // TODO: This will need some rework in the future. (why?)
|
|
|
- case CommandId::SUBMIT_GPU_CMDLIST: {
|
|
|
- auto& params = command.submit_gpu_cmdlist;
|
|
|
-
|
|
|
- if (params.do_flush) {
|
|
|
- // This flag flushes the command list (params.address, params.size) from the cache.
|
|
|
- // Command lists are not processed by the hardware renderer, so we don't need to
|
|
|
- // actually flush them in Citra.
|
|
|
- }
|
|
|
-
|
|
|
- WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(command_processor_config.address)),
|
|
|
- Memory::VirtualToPhysicalAddress(params.address) >> 3);
|
|
|
- WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(command_processor_config.size)),
|
|
|
- params.size);
|
|
|
-
|
|
|
- // TODO: Not sure if we are supposed to always write this .. seems to trigger processing
|
|
|
- // though
|
|
|
- WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(command_processor_config.trigger)), 1);
|
|
|
-
|
|
|
- // TODO(yuriks): Figure out the meaning of the `flags` field.
|
|
|
-
|
|
|
- break;
|
|
|
- }
|
|
|
-
|
|
|
- // It's assumed that the two "blocks" behave equivalently.
|
|
|
- // Presumably this is done simply to allow two memory fills to run in parallel.
|
|
|
- case CommandId::SET_MEMORY_FILL: {
|
|
|
- auto& params = command.memory_fill;
|
|
|
-
|
|
|
- if (params.start1 != 0) {
|
|
|
- WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[0].address_start)),
|
|
|
- Memory::VirtualToPhysicalAddress(params.start1) >> 3);
|
|
|
- WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[0].address_end)),
|
|
|
- Memory::VirtualToPhysicalAddress(params.end1) >> 3);
|
|
|
- WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[0].value_32bit)),
|
|
|
- params.value1);
|
|
|
- WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[0].control)),
|
|
|
- params.control1);
|
|
|
- }
|
|
|
-
|
|
|
- if (params.start2 != 0) {
|
|
|
- WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[1].address_start)),
|
|
|
- Memory::VirtualToPhysicalAddress(params.start2) >> 3);
|
|
|
- WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[1].address_end)),
|
|
|
- Memory::VirtualToPhysicalAddress(params.end2) >> 3);
|
|
|
- WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[1].value_32bit)),
|
|
|
- params.value2);
|
|
|
- WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[1].control)),
|
|
|
- params.control2);
|
|
|
- }
|
|
|
- break;
|
|
|
- }
|
|
|
-
|
|
|
- case CommandId::SET_DISPLAY_TRANSFER: {
|
|
|
- auto& params = command.display_transfer;
|
|
|
- WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.input_address)),
|
|
|
- Memory::VirtualToPhysicalAddress(params.in_buffer_address) >> 3);
|
|
|
- WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.output_address)),
|
|
|
- Memory::VirtualToPhysicalAddress(params.out_buffer_address) >> 3);
|
|
|
- WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.input_size)),
|
|
|
- params.in_buffer_size);
|
|
|
- WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.output_size)),
|
|
|
- params.out_buffer_size);
|
|
|
- WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.flags)),
|
|
|
- params.flags);
|
|
|
- WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.trigger)), 1);
|
|
|
- break;
|
|
|
- }
|
|
|
-
|
|
|
- case CommandId::SET_TEXTURE_COPY: {
|
|
|
- auto& params = command.texture_copy;
|
|
|
- WriteGPURegister((u32)GPU_REG_INDEX(display_transfer_config.input_address),
|
|
|
- Memory::VirtualToPhysicalAddress(params.in_buffer_address) >> 3);
|
|
|
- WriteGPURegister((u32)GPU_REG_INDEX(display_transfer_config.output_address),
|
|
|
- Memory::VirtualToPhysicalAddress(params.out_buffer_address) >> 3);
|
|
|
- WriteGPURegister((u32)GPU_REG_INDEX(display_transfer_config.texture_copy.size),
|
|
|
- params.size);
|
|
|
- WriteGPURegister((u32)GPU_REG_INDEX(display_transfer_config.texture_copy.input_size),
|
|
|
- params.in_width_gap);
|
|
|
- WriteGPURegister((u32)GPU_REG_INDEX(display_transfer_config.texture_copy.output_size),
|
|
|
- params.out_width_gap);
|
|
|
- WriteGPURegister((u32)GPU_REG_INDEX(display_transfer_config.flags), params.flags);
|
|
|
-
|
|
|
- // NOTE: Actual GSP ORs 1 with current register instead of overwriting. Doesn't seem to
|
|
|
- // matter.
|
|
|
- WriteGPURegister((u32)GPU_REG_INDEX(display_transfer_config.trigger), 1);
|
|
|
- break;
|
|
|
- }
|
|
|
-
|
|
|
- case CommandId::CACHE_FLUSH: {
|
|
|
- // NOTE: Rasterizer flushing handled elsewhere in CPU read/write and other GPU handlers
|
|
|
- // Use command.cache_flush.regions to implement this handler
|
|
|
- break;
|
|
|
- }
|
|
|
-
|
|
|
- default:
|
|
|
- LOG_ERROR(Service_GSP, "unknown command 0x%08X", (int)command.id.Value());
|
|
|
- }
|
|
|
-
|
|
|
- if (Pica::g_debug_context)
|
|
|
- Pica::g_debug_context->OnEvent(Pica::DebugContext::Event::GSPCommandProcessed,
|
|
|
- (void*)&command);
|
|
|
-}
|
|
|
-
|
|
|
-/**
|
|
|
- * GSP_GPU::SetLcdForceBlack service function
|
|
|
- *
|
|
|
- * Enable or disable REG_LCDCOLORFILL with the color black.
|
|
|
- *
|
|
|
- * Inputs:
|
|
|
- * 1: Black color fill flag (0 = don't fill, !0 = fill)
|
|
|
- * Outputs:
|
|
|
- * 1: Result code
|
|
|
- */
|
|
|
-static void SetLcdForceBlack(Interface* self) {
|
|
|
- u32* cmd_buff = Kernel::GetCommandBuffer();
|
|
|
-
|
|
|
- bool enable_black = cmd_buff[1] != 0;
|
|
|
- LCD::Regs::ColorFill data = {0};
|
|
|
-
|
|
|
- // Since data is already zeroed, there is no need to explicitly set
|
|
|
- // the color to black (all zero).
|
|
|
- data.is_enabled.Assign(enable_black);
|
|
|
-
|
|
|
- LCD::Write(HW::VADDR_LCD + 4 * LCD_REG_INDEX(color_fill_top), data.raw); // Top LCD
|
|
|
- LCD::Write(HW::VADDR_LCD + 4 * LCD_REG_INDEX(color_fill_bottom), data.raw); // Bottom LCD
|
|
|
-
|
|
|
- cmd_buff[1] = RESULT_SUCCESS.raw;
|
|
|
+ UNIMPLEMENTED();
|
|
|
}
|
|
|
|
|
|
-/// This triggers handling of the GX command written to the command buffer in shared memory.
|
|
|
-static void TriggerCmdReqQueue(Interface* self) {
|
|
|
- // Iterate through each thread's command queue...
|
|
|
- for (unsigned thread_id = 0; thread_id < 0x4; ++thread_id) {
|
|
|
- CommandBuffer* command_buffer = (CommandBuffer*)GetCommandBuffer(thread_id);
|
|
|
-
|
|
|
- // Iterate through each command...
|
|
|
- for (unsigned i = 0; i < command_buffer->number_commands; ++i) {
|
|
|
- g_debugger.GXCommandProcessed((u8*)&command_buffer->commands[i]);
|
|
|
-
|
|
|
- // Decode and execute command
|
|
|
- ExecuteCommand(command_buffer->commands[i], thread_id);
|
|
|
-
|
|
|
- // Indicates that command has completed
|
|
|
- command_buffer->number_commands.Assign(command_buffer->number_commands - 1);
|
|
|
- }
|
|
|
- }
|
|
|
-
|
|
|
- u32* cmd_buff = Kernel::GetCommandBuffer();
|
|
|
- cmd_buff[1] = 0; // No error
|
|
|
-}
|
|
|
-
|
|
|
-/**
|
|
|
- * GSP_GPU::ImportDisplayCaptureInfo service function
|
|
|
- *
|
|
|
- * Returns information about the current framebuffer state
|
|
|
- *
|
|
|
- * Inputs:
|
|
|
- * 0: Header 0x00180000
|
|
|
- * Outputs:
|
|
|
- * 0: Header Code[0x00180240]
|
|
|
- * 1: Result code
|
|
|
- * 2: Left framebuffer virtual address for the main screen
|
|
|
- * 3: Right framebuffer virtual address for the main screen
|
|
|
- * 4: Main screen framebuffer format
|
|
|
- * 5: Main screen framebuffer width
|
|
|
- * 6: Left framebuffer virtual address for the bottom screen
|
|
|
- * 7: Right framebuffer virtual address for the bottom screen
|
|
|
- * 8: Bottom screen framebuffer format
|
|
|
- * 9: Bottom screen framebuffer width
|
|
|
- */
|
|
|
-static void ImportDisplayCaptureInfo(Interface* self) {
|
|
|
- u32* cmd_buff = Kernel::GetCommandBuffer();
|
|
|
-
|
|
|
- // TODO(Subv): We're always returning the framebuffer structures for thread_id = 0,
|
|
|
- // because we only support a single running application at a time.
|
|
|
- // This should always return the framebuffer data that is currently displayed on the screen.
|
|
|
-
|
|
|
- u32 thread_id = 0;
|
|
|
-
|
|
|
- FrameBufferUpdate* top_screen = GetFrameBufferInfo(thread_id, 0);
|
|
|
- FrameBufferUpdate* bottom_screen = GetFrameBufferInfo(thread_id, 1);
|
|
|
-
|
|
|
- cmd_buff[0] = IPC::MakeHeader(0x18, 0x9, 0);
|
|
|
- cmd_buff[1] = RESULT_SUCCESS.raw;
|
|
|
- // Top Screen
|
|
|
- cmd_buff[2] = top_screen->framebuffer_info[top_screen->index].address_left;
|
|
|
- cmd_buff[3] = top_screen->framebuffer_info[top_screen->index].address_right;
|
|
|
- cmd_buff[4] = top_screen->framebuffer_info[top_screen->index].format;
|
|
|
- cmd_buff[5] = top_screen->framebuffer_info[top_screen->index].stride;
|
|
|
- // Bottom Screen
|
|
|
- cmd_buff[6] = bottom_screen->framebuffer_info[bottom_screen->index].address_left;
|
|
|
- cmd_buff[7] = bottom_screen->framebuffer_info[bottom_screen->index].address_right;
|
|
|
- cmd_buff[8] = bottom_screen->framebuffer_info[bottom_screen->index].format;
|
|
|
- cmd_buff[9] = bottom_screen->framebuffer_info[bottom_screen->index].stride;
|
|
|
-
|
|
|
- LOG_WARNING(Service_GSP, "called");
|
|
|
-}
|
|
|
-
|
|
|
-/**
|
|
|
- * GSP_GPU::AcquireRight service function
|
|
|
- * Outputs:
|
|
|
- * 1: Result code
|
|
|
- */
|
|
|
-static void AcquireRight(Interface* self) {
|
|
|
- u32* cmd_buff = Kernel::GetCommandBuffer();
|
|
|
-
|
|
|
- gpu_right_acquired = true;
|
|
|
-
|
|
|
- cmd_buff[1] = RESULT_SUCCESS.raw;
|
|
|
-
|
|
|
- LOG_WARNING(Service_GSP, "called");
|
|
|
-}
|
|
|
-
|
|
|
-/**
|
|
|
- * GSP_GPU::ReleaseRight service function
|
|
|
- * Outputs:
|
|
|
- * 1: Result code
|
|
|
- */
|
|
|
-static void ReleaseRight(Interface* self) {
|
|
|
- u32* cmd_buff = Kernel::GetCommandBuffer();
|
|
|
-
|
|
|
- gpu_right_acquired = false;
|
|
|
-
|
|
|
- cmd_buff[1] = RESULT_SUCCESS.raw;
|
|
|
-
|
|
|
- LOG_WARNING(Service_GSP, "called");
|
|
|
-}
|
|
|
-
|
|
|
-/**
|
|
|
- * GSP_GPU::StoreDataCache service function
|
|
|
- *
|
|
|
- * This Function is a no-op, We aren't emulating the CPU cache any time soon.
|
|
|
- *
|
|
|
- * Inputs:
|
|
|
- * 0 : Header code [0x001F0082]
|
|
|
- * 1 : Address
|
|
|
- * 2 : Size
|
|
|
- * 3 : Value 0, some descriptor for the KProcess Handle
|
|
|
- * 4 : KProcess handle
|
|
|
- * Outputs:
|
|
|
- * 1 : Result of function, 0 on success, otherwise error code
|
|
|
- */
|
|
|
-static void StoreDataCache(Interface* self) {
|
|
|
- u32* cmd_buff = Kernel::GetCommandBuffer();
|
|
|
- u32 address = cmd_buff[1];
|
|
|
- u32 size = cmd_buff[2];
|
|
|
- u32 process = cmd_buff[4];
|
|
|
-
|
|
|
- cmd_buff[0] = IPC::MakeHeader(0x1F, 0x1, 0);
|
|
|
- cmd_buff[1] = RESULT_SUCCESS.raw; // No error
|
|
|
-
|
|
|
- LOG_DEBUG(Service_GSP, "(STUBBED) called address=0x%08X, size=0x%08X, process=0x%08X", address,
|
|
|
- size, process);
|
|
|
-}
|
|
|
-
|
|
|
-const Interface::FunctionInfo FunctionTable[] = {
|
|
|
- {0x00010082, WriteHWRegs, "WriteHWRegs"},
|
|
|
- {0x00020084, WriteHWRegsWithMask, "WriteHWRegsWithMask"},
|
|
|
- {0x00030082, nullptr, "WriteHWRegRepeat"},
|
|
|
- {0x00040080, ReadHWRegs, "ReadHWRegs"},
|
|
|
- {0x00050200, SetBufferSwap, "SetBufferSwap"},
|
|
|
- {0x00060082, nullptr, "SetCommandList"},
|
|
|
- {0x000700C2, nullptr, "RequestDma"},
|
|
|
- {0x00080082, FlushDataCache, "FlushDataCache"},
|
|
|
- {0x00090082, nullptr, "InvalidateDataCache"},
|
|
|
- {0x000A0044, nullptr, "RegisterInterruptEvents"},
|
|
|
- {0x000B0040, SetLcdForceBlack, "SetLcdForceBlack"},
|
|
|
- {0x000C0000, TriggerCmdReqQueue, "TriggerCmdReqQueue"},
|
|
|
- {0x000D0140, nullptr, "SetDisplayTransfer"},
|
|
|
- {0x000E0180, nullptr, "SetTextureCopy"},
|
|
|
- {0x000F0200, nullptr, "SetMemoryFill"},
|
|
|
- {0x00100040, SetAxiConfigQoSMode, "SetAxiConfigQoSMode"},
|
|
|
- {0x00110040, nullptr, "SetPerfLogMode"},
|
|
|
- {0x00120000, nullptr, "GetPerfLog"},
|
|
|
- {0x00130042, RegisterInterruptRelayQueue, "RegisterInterruptRelayQueue"},
|
|
|
- {0x00140000, UnregisterInterruptRelayQueue, "UnregisterInterruptRelayQueue"},
|
|
|
- {0x00150002, nullptr, "TryAcquireRight"},
|
|
|
- {0x00160042, AcquireRight, "AcquireRight"},
|
|
|
- {0x00170000, ReleaseRight, "ReleaseRight"},
|
|
|
- {0x00180000, ImportDisplayCaptureInfo, "ImportDisplayCaptureInfo"},
|
|
|
- {0x00190000, nullptr, "SaveVramSysArea"},
|
|
|
- {0x001A0000, nullptr, "RestoreVramSysArea"},
|
|
|
- {0x001B0000, nullptr, "ResetGpuCore"},
|
|
|
- {0x001C0040, nullptr, "SetLedForceOff"},
|
|
|
- {0x001D0040, nullptr, "SetTestCommand"},
|
|
|
- {0x001E0080, nullptr, "SetInternalPriorities"},
|
|
|
- {0x001F0082, StoreDataCache, "StoreDataCache"},
|
|
|
-};
|
|
|
-
|
|
|
GSP_GPU::GSP_GPU() {
|
|
|
- Register(FunctionTable);
|
|
|
-
|
|
|
- g_interrupt_event = nullptr;
|
|
|
-
|
|
|
- using Kernel::MemoryPermission;
|
|
|
- g_shared_memory = Kernel::SharedMemory::Create(nullptr, 0x1000, MemoryPermission::ReadWrite,
|
|
|
- MemoryPermission::ReadWrite, 0,
|
|
|
- Kernel::MemoryRegion::BASE, "GSP:SharedMemory");
|
|
|
-
|
|
|
- g_thread_id = 0;
|
|
|
- gpu_right_acquired = false;
|
|
|
- first_initialization = true;
|
|
|
}
|
|
|
|
|
|
GSP_GPU::~GSP_GPU() {
|
|
|
- g_interrupt_event = nullptr;
|
|
|
- g_shared_memory = nullptr;
|
|
|
- gpu_right_acquired = false;
|
|
|
}
|
|
|
|
|
|
} // namespace GSP
|