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@@ -109,6 +109,8 @@ union OpCode {
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FSETP_R = 0x5BB,
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FSETP_R = 0x5BB,
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FSETP_C = 0x4BB,
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FSETP_C = 0x4BB,
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+ FSETP_IMM = 0x36B,
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+ FSETP_NEG_IMM = 0x37B,
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EXIT = 0xE30,
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EXIT = 0xE30,
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KIL = 0xE33,
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KIL = 0xE33,
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@@ -124,6 +126,7 @@ union OpCode {
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Ffma,
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Ffma,
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Flow,
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Flow,
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Memory,
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Memory,
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+ FloatPredicate,
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Unknown,
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Unknown,
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};
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};
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@@ -164,6 +167,9 @@ union OpCode {
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case Id::FSETP_C:
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case Id::FSETP_C:
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case Id::KIL:
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case Id::KIL:
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return op4;
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return op4;
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+ case Id::FSETP_IMM:
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+ case Id::FSETP_NEG_IMM:
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+ return Id::FSETP_IMM;
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}
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}
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switch (op5) {
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switch (op5) {
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@@ -241,8 +247,9 @@ union OpCode {
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info_table[Id::FMUL_C] = {Type::Arithmetic, "fmul_c"};
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info_table[Id::FMUL_C] = {Type::Arithmetic, "fmul_c"};
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info_table[Id::FMUL_IMM] = {Type::Arithmetic, "fmul_imm"};
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info_table[Id::FMUL_IMM] = {Type::Arithmetic, "fmul_imm"};
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info_table[Id::FMUL32_IMM] = {Type::Arithmetic, "fmul32_imm"};
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info_table[Id::FMUL32_IMM] = {Type::Arithmetic, "fmul32_imm"};
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- info_table[Id::FSETP_C] = {Type::Arithmetic, "fsetp_c"};
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- info_table[Id::FSETP_R] = {Type::Arithmetic, "fsetp_r"};
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+ info_table[Id::FSETP_C] = {Type::FloatPredicate, "fsetp_c"};
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+ info_table[Id::FSETP_R] = {Type::FloatPredicate, "fsetp_r"};
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+ info_table[Id::FSETP_IMM] = {Type::FloatPredicate, "fsetp_imm"};
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info_table[Id::EXIT] = {Type::Trivial, "exit"};
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info_table[Id::EXIT] = {Type::Trivial, "exit"};
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info_table[Id::IPA] = {Type::Trivial, "ipa"};
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info_table[Id::IPA] = {Type::Trivial, "ipa"};
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info_table[Id::KIL] = {Type::Flow, "kil"};
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info_table[Id::KIL] = {Type::Flow, "kil"};
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@@ -286,7 +293,23 @@ namespace Shader {
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enum class Pred : u64 {
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enum class Pred : u64 {
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UnusedIndex = 0x7,
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UnusedIndex = 0x7,
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- NeverExecute = 0xf,
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+ NeverExecute = 0xF,
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+};
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+
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+enum class PredCondition : u64 {
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+ LessThan = 1,
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+ Equal = 2,
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+ LessEqual = 3,
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+ GreaterThan = 4,
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+ NotEqual = 5,
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+ GreaterEqual = 6,
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+ // TODO(Subv): Other condition types
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+};
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+
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+enum class PredOperation : u64 {
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+ And = 0,
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+ Or = 1,
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+ Xor = 2,
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};
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};
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enum class SubOp : u64 {
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enum class SubOp : u64 {
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@@ -346,6 +369,20 @@ union Instruction {
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BitField<49, 1, u64> negate_c;
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BitField<49, 1, u64> negate_c;
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} ffma;
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} ffma;
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+ union {
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+ BitField<0, 3, u64> pred0;
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+ BitField<3, 3, u64> pred3;
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+ BitField<7, 1, u64> abs_a;
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+ BitField<39, 3, u64> pred39;
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+ BitField<42, 1, u64> neg_pred;
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+ BitField<43, 1, u64> neg_a;
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+ BitField<44, 1, u64> abs_b;
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+ BitField<45, 2, PredOperation> op;
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+ BitField<47, 1, u64> ftz;
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+ BitField<48, 4, PredCondition> cond;
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+ BitField<56, 1, u64> neg_b;
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+ } fsetp;
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+
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BitField<61, 1, u64> is_b_imm;
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BitField<61, 1, u64> is_b_imm;
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BitField<60, 1, u64> is_b_gpr;
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BitField<60, 1, u64> is_b_gpr;
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BitField<59, 1, u64> is_c_gpr;
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BitField<59, 1, u64> is_c_gpr;
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