|
|
@@ -126,6 +126,15 @@ union Sampler {
|
|
|
u64 value{};
|
|
|
};
|
|
|
|
|
|
+union Image {
|
|
|
+ Image() = default;
|
|
|
+
|
|
|
+ constexpr explicit Image(u64 value) : value{value} {}
|
|
|
+
|
|
|
+ BitField<36, 13, u64> index;
|
|
|
+ u64 value;
|
|
|
+};
|
|
|
+
|
|
|
} // namespace Tegra::Shader
|
|
|
|
|
|
namespace std {
|
|
|
@@ -344,6 +353,26 @@ enum class TextureMiscMode : u64 {
|
|
|
PTP,
|
|
|
};
|
|
|
|
|
|
+enum class SurfaceDataMode : u64 {
|
|
|
+ P = 0,
|
|
|
+ D_BA = 1,
|
|
|
+};
|
|
|
+
|
|
|
+enum class OutOfBoundsStore : u64 {
|
|
|
+ Ignore = 0,
|
|
|
+ Clamp = 1,
|
|
|
+ Trap = 2,
|
|
|
+};
|
|
|
+
|
|
|
+enum class ImageType : u64 {
|
|
|
+ Texture1D = 0,
|
|
|
+ TextureBuffer = 1,
|
|
|
+ Texture1DArray = 2,
|
|
|
+ Texture2D = 3,
|
|
|
+ Texture2DArray = 4,
|
|
|
+ Texture3D = 5,
|
|
|
+};
|
|
|
+
|
|
|
enum class IsberdMode : u64 {
|
|
|
None = 0,
|
|
|
Patch = 1,
|
|
|
@@ -398,7 +427,7 @@ enum class LmemLoadCacheManagement : u64 {
|
|
|
CV = 3,
|
|
|
};
|
|
|
|
|
|
-enum class LmemStoreCacheManagement : u64 {
|
|
|
+enum class StoreCacheManagement : u64 {
|
|
|
Default = 0,
|
|
|
CG = 1,
|
|
|
CS = 2,
|
|
|
@@ -811,7 +840,7 @@ union Instruction {
|
|
|
} ld_l;
|
|
|
|
|
|
union {
|
|
|
- BitField<44, 2, LmemStoreCacheManagement> cache_management;
|
|
|
+ BitField<44, 2, StoreCacheManagement> cache_management;
|
|
|
} st_l;
|
|
|
|
|
|
union {
|
|
|
@@ -1294,6 +1323,35 @@ union Instruction {
|
|
|
}
|
|
|
} tlds;
|
|
|
|
|
|
+ union {
|
|
|
+ BitField<24, 2, StoreCacheManagement> cache_management;
|
|
|
+ BitField<33, 3, ImageType> image_type;
|
|
|
+ BitField<49, 2, OutOfBoundsStore> out_of_bounds_store;
|
|
|
+ BitField<51, 1, u64> is_immediate;
|
|
|
+ BitField<52, 1, SurfaceDataMode> mode;
|
|
|
+
|
|
|
+ BitField<20, 3, StoreType> store_data_layout;
|
|
|
+ BitField<20, 4, u64> component_mask_selector;
|
|
|
+
|
|
|
+ bool IsComponentEnabled(std::size_t component) const {
|
|
|
+ ASSERT(mode == SurfaceDataMode::P);
|
|
|
+ constexpr u8 R = 0b0001;
|
|
|
+ constexpr u8 G = 0b0010;
|
|
|
+ constexpr u8 B = 0b0100;
|
|
|
+ constexpr u8 A = 0b1000;
|
|
|
+ constexpr std::array<u8, 16> mask = {
|
|
|
+ 0, (R), (G), (R | G), (B), (R | B),
|
|
|
+ (G | B), (R | G | B), (A), (R | A), (G | A), (R | G | A),
|
|
|
+ (B | A), (R | B | A), (G | B | A), (R | G | B | A)};
|
|
|
+ return std::bitset<4>{mask.at(component_mask_selector)}.test(component);
|
|
|
+ }
|
|
|
+
|
|
|
+ StoreType GetStoreDataLayout() const {
|
|
|
+ ASSERT(mode == SurfaceDataMode::D_BA);
|
|
|
+ return store_data_layout;
|
|
|
+ }
|
|
|
+ } sust;
|
|
|
+
|
|
|
union {
|
|
|
BitField<20, 24, u64> target;
|
|
|
BitField<5, 1, u64> constant_buffer;
|
|
|
@@ -1385,6 +1443,7 @@ union Instruction {
|
|
|
|
|
|
Attribute attribute;
|
|
|
Sampler sampler;
|
|
|
+ Image image;
|
|
|
|
|
|
u64 value;
|
|
|
};
|
|
|
@@ -1428,6 +1487,7 @@ public:
|
|
|
TLD4S, // Texture Load 4 with scalar / non - vec4 source / destinations
|
|
|
TMML_B, // Texture Mip Map Level
|
|
|
TMML, // Texture Mip Map Level
|
|
|
+ SUST, // Surface Store
|
|
|
EXIT,
|
|
|
IPA,
|
|
|
OUT_R, // Emit vertex/primitive
|
|
|
@@ -1558,6 +1618,7 @@ public:
|
|
|
Synch,
|
|
|
Memory,
|
|
|
Texture,
|
|
|
+ Image,
|
|
|
FloatSet,
|
|
|
FloatSetPredicate,
|
|
|
IntegerSet,
|
|
|
@@ -1703,6 +1764,7 @@ private:
|
|
|
INST("1101111100------", Id::TLD4S, Type::Texture, "TLD4S"),
|
|
|
INST("110111110110----", Id::TMML_B, Type::Texture, "TMML_B"),
|
|
|
INST("1101111101011---", Id::TMML, Type::Texture, "TMML"),
|
|
|
+ INST("11101011001-----", Id::SUST, Type::Image, "SUST"),
|
|
|
INST("11100000--------", Id::IPA, Type::Trivial, "IPA"),
|
|
|
INST("1111101111100---", Id::OUT_R, Type::Trivial, "OUT_R"),
|
|
|
INST("1110111111010---", Id::ISBERD, Type::Trivial, "ISBERD"),
|